Infineon Technologies Ag

Qimonda Ag

Peter Weitz

Jochen Thomas

Jurgen Grafe

Jens G Pohl

Harry Hedler

Justus Kuhn

Ingo Wennemuth

Wolfgang Hetzel

Sylke Ludewig

A semiconductor component () has an interposer substrate () as stack element of a semiconductor component stack (). The interposer substrate () has, on one of the interposer substrate sides (), a semiconductor chip protected by plastics composition () in its side edges (). An interposer structure () partly covered by a plastics composition () is arranged on the interposer side () opposite to the semiconductor chip (). Edge regions () of the interposer substrate () remain free of any plastics composition () and have, on both interposer sides () external contact pads () which are electrically connected to one another via through contacts ().

Semiconductor component comprising an interposer substrate

An apparatus and a method of manufacture for a stacked-die assembly. A first die is placed on a substrate such that the backside of the die, i.e., the side opposite the side with the bond pads, is coupled to the substrate, preferably by an adhesive. Wire leads electrically couple the bond pads of the first die to contacts on the substrate. A second die is placed on the first die, and wire leads electrically couple the bond pads of the second die to contacts on the substrate. Preferably, a spacer is placed between the first die and the second die. Additional dies may be stacked on the second die.

Integrated circuit with re-route layer and stacked die assembly

A semiconductor module having an internal semiconductor chip stack on a wiring substrate is disclosed. In one embodiment, the semiconductor chip stack has semiconductor chips which are arranged such that they are offset, the semiconductor chips having bonding connection pads in at least one edge region of their active top side. These bonding connection pads are electrically connected to the wiring substrate via bonding connections. In this case, the semiconductor chips are stacked on top of one another in an offset manner such that the bonding connection pads remain free of a semiconductor chip which is stacked on top of them. In this case, the semiconductor chips may be identical silicon chips which may differ, for example in pairs, in terms of their wiring structure for the centrally arranged contact areas in different edge regions.

Semiconductor module having an internal semiconductor chip stack, and method for producing said semiconductor module

A method and a device for reducing addresses of faulty memory cells compare addresses of faulty memory cells, as first fault addresses, with addresses of word lines or bit lines which are to be completely repaired, these addresses are referred to as second fault addresses. If the first fault address corresponds to the second fault address, the first fault address is deleted and not further processed. In a second comparison, it is determined, by reference to the number of non-deleted first fault addresses, whether an address of a word line or bit line is used as a new second fault address for the first comparison method. The number of addresses of faulty memory cells are thus reduced.

Device and method for reducing the number of addresses of faulty memory cells

An integrated magnetoresisitive semiconductor memory configuration has MRAM memory cells located at crossover points of selection lines that are embedded in different, mutually separate line planes. A read/write current can be impressed in respective selection lines for writing to each MRAM memory cell and for reading an information item written therein. In this magnetoresistive semiconductor memory configuration, selection lines that serve for reading a cell information item are in each case located in separate first and second line planes in direct contact with the memory cells. A third and a fourth line plane are spatially separated and electrically isolated from the first and second line planes and are occupied by write selection lines for writing a cell information item.

Method for writing to the magnetoresistive memory cells of an integrated magnetoresistive semiconductor memory

An integrated memory including memory cells in a plurality of memory cell blocks, each memory cell block being assigned at least one dedicated data line and a register circuit that can be written from outside the memory. At the start of a test operation, data is stored in the register circuits as reference data. During an access cycle, in each case in each of the memory cell blocks, a respective memory cell or a group of memory cells is selected, a respective read amplifier is activated and, in each of the register circuits, a comparison between the data read out and the reference data is carried out. As a result, the time required for the test operation of the memory is made comparatively low.

Integrated memory with memory cells in a plurality of memory cell blocks, and method of operating such a memory

A circuit configuration for performing a selective changeover of word lines of a memory matrix between an activation potential and a deactivation potential uses selectively addressable drivers. The changeover of a word line input terminal from the activation potential to the deactivation potential is effected through the relevant driver if a deactivation signal is brought to an active state by a timing control circuit. In order to accelerate the deactivation of the word lines, a respectively assigned deactivation auxiliary switch is connected to each of the word lines at at least one terminal remote from the input terminal. The deactivation auxiliary switch is controlled by a timing control circuit such that it connects the remote terminal to the deactivation potential practically at the same instant at which the assigned driver changes the input terminal of the relevant word line from the activation potential over to the deactivation potential.

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Sauerlach, Germany

Peter Weitz