Institute of Microelectronics

Ang Technologies Inc.

Peter S Wang

Yu-Wen Huang

Ulises Olvera-Hernandez

Louis J Guccione

Stephen E Terry

A flip-chip IC package configured for ease of testing comprises a substrate and a plurality of stiffener walls, each stiffener wall carrying an IC, wherein the stiffener walls and ICs are fixed to the substrate with electrical continuity being established between the substrate and the stiffener walls and IC's through conductive bumps (solder bumps or conductive epoxy bumps). The substrate and the stiffener walls include test points on their surfaces, and also include printed electrical circuitry connecting the test points and the conductive bumps. Some of the printed electrical circuitry is arranged to establish paths between test points which facilitate testing of conductivity through the conductive bumps, and which facilitate functional testing of the ICs.

Integrated circuit chip package with test points

A substrate assembly and method of forming the substrate assembly having a very thin form factor and a large amount of manufacturing flexibility. A flexible tape has a number of device blocks. Devices, passive or active, are joined to the device blocks forming a flexible tape assembly and the flexible tape assembly is electrically tested. Substrates are formed having cavities matching the device blocks. The flexible tape assembly is then joined to the substrate such that the devices fit into the cavities, thereby forming a substrate assembly having a very thin form factor. The flexible tape can be stored on a reel and the substrates can be formed in an array and cut to the desired size providing manufacturing flexibility.

Very thin multi-chip package and method of mass producing the same

Very thin multi-chip-package and method of mass producing the same

A process of making a multilayer printed wiring board assembly. The process includes the steps of providing a first and a second substrate made of a dielectric material; depositing a first wiring pattern on the first substrate and a second wiring pattern on the second substrate with a conductive material; depositing a dielectric material on the first and second wiring patterns and defining a via connecting zone on the first and the second wiring pattern for communicating signals between the first and the second wiring pattern by exposing a selective portion of the first and second wiring patterns; depositing a conductive bonding material on the via connecting zone of one of the first and the second wiring pattern; arranging the first and the second substrate in sandwiched juxtaposition such that the via connecting zones of the first and the second wiring pattern are opposite each other and in substantial alignment with each other so that the conductive bonding material deposited on the one of the via connecting zones contacts another one of the via connecting zones; and curing the deposited bonding material thereby forming a conductive joint connecting the first and the second via connecting zones.

Growing community of inventors

Basking Ridge, NJ, United States of America

Peter S Wang