Infineon Technologies Ag

Peter Ossimitz

Gottfried Beer

Dirk Hesidenz

Tobias Jacobs

Matthias Von Daak

Jens Barrenscheen

Juergen Hoegerl

Markus Dinkel

Juergen Schaefer

Stefan Macheiner

Ralf Arnold

Liu Chen

Roderick McConnell

Andreas Munding

Robert Bauer

Gavin Gibson

Matthias Van Daak

A semiconductor chip includes a semiconductor body having an active device region, one or more metallization layers insulated from the semiconductor body and configured to carry one or more of ground, power and signals to the active device region, and a plurality of contact terminals formed in or disposed on an outermost one of the metallization layers and configured to provide external electrical access to the semiconductor chip. A minimum distance between adjacent ones of the contact terminals is defined for the semiconductor chip. One or more groups of adjacent ones of the contact terminals have an electrical or functional commonality and a pitch less than the defined minimum distance. A single shared solder joint can connect two or more of the contact terminals of the semiconductor chip to one or more of contact terminals of a substrate such as a circuit board, an interposer or another semiconductor chip.

Semiconductor chip having a dense arrangement of contact terminals

Representative implementations of devices and techniques provide optimized electrical performance of interconnectivity components of multi-layer integrated circuits (IC) such as chip dice, for example. Different layers of the multi-layer IC include contact terminals that may be used to connect to circuits, systems, and carriers external to the IC.

Multi-level chip interconnect

A semiconductor device package includes an electronic component and an electrical interconnect. The electronic component is attached to the electrical interconnect. The electrical interconnect is configured to electrically couple the electronic component to external terminals of the semiconductor device package. The electrical interconnect has a first main face facing the electronic component and a second main face opposite the first main face. The semiconductor device package further includes a first semiconductor chip facing the second main face of the electrical interconnect.

Semiconductor device having a chip under package

The disclosure relates to a circuitry including a first contact connected to a power supply, a first compare unit connected to the first contact and to a first reference signal, wherein the first compare unit is configured to compare a voltage at the first contact with the first reference signal and provide a first output signal for further processing.

Circuitry and method for monitoring a power supply of an electronic device

An electronic device comprises a substrate, at least one electronic chip mounted on and electrically connected to the substrate and being configured as a system control unit for controlling a connected system, a heat removal structure thermally connected to the at least one electronic chip and configured for removing heat generated by the at least one electronic chip upon operation of the electronic device, and an overmolding structure configured for at least partially encapsulating at least the at least one electronic chip and the substrate.

Overmolded substrate-chip arrangement with heat sink

A chip package includes an integrated circuit chip. A first group of terminal pads of the chip package is electrically connected to the integrated circuit chip and a second group of terminal pads of the chip package is electrically connected to the integrated circuit chip. The first and second groups of terminal pads are arranged on a common terminal surface of the chip package. A pad size of a terminal pad of the first group of terminal pads is greater than a pad size of a terminal pad of the second group of terminal pads.

Chip package having terminal pads of different form factors

Embodiments of the present invention relate to a semiconductor chip comprising a plurality of contact pads, which are arranged in an edge area on a surface of the semiconductor chip. In a semiconductor area of the semiconductor chip, every contact pad of the plurality of contact pads has an associated pad cell provided, which includes at least one of a driver or a receiver and is configured to drive output signals or receive input signals on its associated contact pad, if the driver or receiver is connected to the contact pad. Additionally, for a contact pad which is used as a supply contact pad, the driver or receiver of the associated pad cell is not connected to the contact pad or any other contact pad for driving output signals or receiving input signals on the same.

Method for manufacturing a semiconductor chip with each contact pad having a pad cell associated therewith

A chip arrangement may include: a chip including a plurality of electrical nets, wherein each electrical net includes at least one bonding pad; and a plurality of pillars formed on the at least one bonding pad of a majority of the plurality of electrical nets, wherein the plurality of pillars may be configured to connect the at least one bonding pad of the majority of the plurality of electrical nets to a chip-external connection region.

Chip arrangement, and method for forming a chip arrangement

An Integrated Circuit (IC) package comprises a package comprising a first set of pads having a pinout that is compatible with a chip core of a product family. A second set of pads are on substantially the same plane as the first set of pads and outside the package core. The second set of pads is configured to accommodate a circuit outside the chip core. The geometric center of the package core is different from the geometric center of the IC package.

Integrated IC package

A method of producing and testing a chip package is described. The chip package to be produced includes a semiconductor chip containing an integrated circuit and a reinforcing structure attached to the semiconductor chip. Further, the chip package has a lower main face and an upper main face opposite to the lower main face, wherein the lower main face is at least partly formed by an exposed surface of the semiconductor chip and the upper main face is formed by a terminal surface of the reinforcing structure on which external terminal pads of the chip package are arranged. After production, the package is subjected to a package-level burn-in test.

Method of manufacturing and testing a chip package

A method for correcting faults in semiconductor memory components provides an application system having a multichip module () which has a semiconductor memory component () containing a volatile memory and a diverting circuit (). When the application system is being booted up, addresses of faulty memory cells in the semiconductor memory component () are loaded into the multichip module (), with the result that the diverting circuit () diverts access to a memory cell in the replacement data memory if a faulty memory cell in the semiconductor memory component () is accessed.

Semiconductor memory component having a diverting circuit

A semiconductor chip includes a plurality of contact pads, which are arranged in an edge area on a surface of the semiconductor chip. In a semiconductor area of the semiconductor chip, every contact pad of the plurality of contact pads has an associated pad cell provided, which includes at least one of a driver or a receiver and is configured to drive output signals or receive input signals on its associated contact pad, if the driver or receiver is connected to the contact pad. Additionally, for a contact pad which is used as a supply contact pad, the driver or receiver of the associated pad cell is not connected to the contact pad or any other contact pad for driving output signals or receiving input signals on the same.

Semiconductor chip comprising a plurality of contact pads and a plurality of associated pad cells

A device is disclosed for releasably receiving a singulated semiconductor chip having a first main surface and a second main surface opposite the first main surface. The device includes a support structure. At least one elastic element is arranged on the support structure. Electrical contact elements are arranged on the at least one elastic element and adapted to be contacted to the first main surface of the semiconductor chip. A foil is adapted to be arranged over the second main surface of the semiconductor chip.

Device for releasably receiving a semiconductor chip

An electronic element, test system and method of testing an electronic circuit are provided. The electronic circuit has input and output terminals. The input terminals receive a test signal sequence to test the electronic circuit. Actual value signals of a 3-value logic of the electronic circuit are provided at the output terminals in response to the test signal sequence. A comparator circuit has first and second input terminals and an output terminal. Each of the output terminals of the electronic circuit are coupled to a first input terminal. The second input terminals receive desired value signals. The comparator circuit compares the actual value signals with the desired value signals and provides the comparison to the output terminal of the comparator circuit.

Electronic element comprising an electronic circuit which is to be tested and test system arrangement which is used to test the electronic element

A rewiring substrate strip and a method of producing a rewiring substrate strip is disclosed. In one embodiment, the rewiring substrate strip has several semiconductor component positions for semiconductor components. The semiconductor component positions are arranged in rows and columns. In this arrangement, several semiconductor component positions are combined to form one component group. The semiconductor components of a component group are arranged with respect to one another in such a manner that an individual semiconductor component is rotated by 90&#xb0; with respect to four adjacent semiconductor components.

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Munich, Germany

Peter Ossimitz