Isc8 Inc.

Peter Lieu

W Eric Boyd

James S Yamaguchi

Randy Bindrup

A method for fabricating a stackable integrated circuit layer and a device made from the method are disclosed. A stud bump is defined on the contact pad of an integrated circuit die and the stud-bumped die encapsulated in a potting material to define a potted assembly. A predetermined portion of the potting material is removed whereby a portion of the stud bump is exposed. One or more electrically conductive traces are defined on the layer surface and in electrical connection with the stud bump to reroute the integrated circuit contacts to predetermined locations on the layer to provide a stackable neolayer.

Method for fabricating a neo-layer using stud bumped bare die

A method for providing a known good integrated circuit die having enhanced planarity from a prepackaged integrated circuit die having a surface warpage such as in a ball grid array (BGA) package is provided. A partially-depackaged integrated circuit package is affixed to a substrate with a spacer element there between such that the active surface of the die within the partially depackaged integrated circuit die is 'bowed' slightly upwardly to define a convex surface. The exposed encapsulant on the now-convex surface of the mounted, partially-depackaged integrated circuit package is then lapped or ground away to a predetermined depth so that an integrated circuit die is provided having an enhanced planarity and surface uniformity.

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Irvine, CA, United States of America

Peter Lieu