International Business Machines Corporation

Peter John Geiss

Qizhi Liu

Alvin Jose Joseph

Douglas Duane Coolbaugh

Marwan H Khater

Xuefeng Liu

Randy William Mann

James Stuart Dunn

Andreas Daniel Stricker

Stephen Arthur St Onge

Robert J Purtell

Peter B Gray

Joseph R Greco

Richard Steven Kontra

Jae-Sung Rieh

Emily Lanning

Matthew D Gallagher

Son Van Nguyen

Rajendran Krishnasamy

Donald M Kenney

Howard Smith Landis

Bradley Alan Orner

BethAnn Rainey

Mark D Dupuis

Brett A Philips

Arne Watson Ballantine

James William Adkisson

Kirk David Peterson

Herbert Lei Ho

David Louis Harame

James Spiros Nakos

Kathryn Turner Schonenberg

James Gardner Ryan

Seshadri Subbanna

Glen L Miles

Shwu-Jen Jeng

Tina Jane Wagner

Jeffrey D Gilbert

Marc Waine Cantell

Thomas John Licata

James J Quinlivan

Beth Ann Rainey

Donna Kaye Johnson

Robb Allen Johnson

Douglas Brian Hershberger

James J Toomey

Rajesh Chopdekar

Peter B c/o Ibm United Kingdom Ltd Gray

A method of modulating grain size in a polysilicon layer and devices fabricated with the method. The method includes forming the layer of polysilicon on a substrate; and performing an ion implantation of a polysilicon grain size modulating species into the polysilicon layer such that an average resultant grain size of the implanted polysilicon layer after performing a pre-determined anneal is higher or lower than an average resultant grain size than would be obtained after performing the same pre-determined anneal on the polysilicon layer without a polysilicon grain size modulating species ion implant.

Method of controlling grain size in a polysilicon layer and in semiconductor devices having polysilicon structure

Methods for fabricating a heterojunction bipolar transistor having a raised extrinsic base is provided in which the base resistance is reduced by forming a silicide atop the raised extrinsic base that extends to the emitter region in a self-aligned manner. The silicide formation is incorporated into a BiCMOS process flow after the raised extrinsic base has been formed. The present invention also provides a heterojunction bipolar transistor having a raised extrinsic base and a silicide located atop the raised extrinsic base. The silicide atop the raised extrinsic base extends to the emitter in a self-aligned manner. The emitter is separated from the silicide by a spacer.

Methods of base formation in a BiCOMS process

Disclosed is a bipolar complementary metal oxide semiconductor (BiCMOS) or NPN/PNP device that has a collector, an intrinsic base above the collector, shallow trench isolation regions adjacent the collector, a raised extrinsic base above the intrinsic base, a T-shaped emitter above the extrinsic base, spacers adjacent the emitter, and a silicide layer that is separated from the emitter by the spacers.

Method of base formation in a BiCMOS process

A heterojunction bipolar transistor is formed in a semiconductor substrate of a first conductivity type including a collector region. A base region is formed on the substrate and an emitter region is formed over the base region. At least one of the collector, base and emitter regions includes a first region doped with an impurity having a first concentration and a second region doped with the impurity having a second concentration. Noise performance and reliability of the heterojunction bipolar transistor is improved without degrading ac performance.

Method of fabrication for SiGe heterojunction bipolar transistor (HBT)

A heterobipolar transistor (HBT) for high-speed BiCMOS applications is provided in which the collector resistance, Rc, is lowered by providing a buried refractory metal silicide layer underneath the shallow trench isolation region on the subcollector of the device. Specifically, the HBT of the present invention includes a substrate including at least a subcollector; a buried refractory metal silicide layer located on the subcollector; and a shallow trench isolation region located on a surface of the buried refractory metal silicide layer. The present invention also provides a method of fabricating such a HBT. The method includes forming a buried refractory metal silicide underneath the shallow trench isolation region on the subcollector of the device.

Method of collector formation in BiCMOS technology

Methods of base formation in a BiCMOS process

SiGe heterojunction bipolar transistor (HBT)

A method of modulating grain size in a polysilicon layer and devices fabricated with the method. The method comprises forming the layer of polysilicon on a substrate; and performing an ion implantation of a polysilicon grain size modulating species into the polysilicon layer such that an average resultant grain size of the implanted polysilicon layer after performing a pre-determined anneal is higher or lower than an average resultant grain size than would be obtained after performing the same pre-determined anneal on the polysilicon layer without a polysilicon grain size modulating species ion implant.

Method of controlling grain size in a polysilicon layer and in semiconductor devices having polysilicon structures

A method for removing silicon dioxide residuals is disclosed. The method includes reacting a portion of a silicon dioxide layer (i.e., oxide) to form a reaction product layer, removing the reaction product layer and annealing in an environment to remove oxide residuals. The method finds application in a variety of semiconductor fabrication processes including, for example, fabrication of a vertical HBT or silicon-to-silicon interface without an oxide interface.

Silicon dioxide removing method

A SiGe bipolar transistor including a semiconductor substrate having a collector and sub-collector region formed therein, wherein the collector and sub-collector are formed between isolation regions that are also present in the substrate is provided. Each isolation region includes a recessed surface and a non-recessed surface which are formed utilizing lithography and etching. A SiGe layer is formed on the substrate as well as the recessed non-recessed surfaces of each isolation region, the SiGe layer includes polycrystalline Si regions and a SiGe base region. A patterned insulator layer is formed on the SiGe base region; and an emitter is formed on the patterned insulator layer and in contact with the SiGe base region through an emitter window opening.

STI pull-down to control SiGe facet growth

Disclosed is a bipolar complementary metal oxide semiconductor (BiCMOS) or NPN/PNP device that has a collector, an intrinsic base above the collector, shallow trench isolation regions adjacent the collector, a raised extrinsic base above the intrinsic base, a T-shaped emitter above the extrinic base, spacers adjacent the emitter, and a silicide layer that is separated from the emitter by the spacers.

Sti pull-down to control SiGe facet growth

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Underhill, VT, United States of America

Peter John Geiss