Globalfoundries Inc.

Advanced Micro Devices Corporation

Globalfoundries U.S. Inc.

Peter Javorka

Jan Hoentschel

Stefan Flachowsky

Ralf Richter

Stephan Kronholz

Maciej Wiatr

Roman Boschke

Manfred Horstmann

Stephan-Detlef Kronholz

Andy C Wei

Joe Bloomquist

Thilo Scheiper

Thorsten E Kammler

Juergen Faul

Sven Beyer

Hans-Juergen Thees

Frank Wirbeleit

Christoph Schwan

Gert Burbach

Gunda Beernink

Markus Forsberg

Karla Romero

Philipp Steinmann

Kai Frohberg

Karsten Wieczorek

Markus Lenski

Rolf Stephan

Mohit Bajaj

Andreas Kurz

Martin Gerhardt

Andreas Gehring

Clemens Fitz

Glyn Braithwaite

Christian Krueger

Nicolas Sassiat

Casey Scott

Matthias Kessler

Kerstin Ruttloff

Steven Langdon

Chung Foong Tan

Ruchil Kumar Jain

Dominik M Kleimaier

Gerd Zschätzsch

Jan Höntschel

Bastian Haussdoerfer

Steffen A Sichler

Ali Icel

Felix Holzmüller

Sergej Mutas

Sylvain Henri Baudot

Falong Zhou

Clemens Wündisch

Prashanth Paramahans Manik

Avinash Lahgere

Structures for a field-effect transistor and methods of forming a structure for a field-effect transistor. The structure comprises a silicon-on-insulator substrate including a semiconductor substrate, a dielectric layer on the semiconductor substrate, and a semiconductor layer on the dielectric layer. The structure further comprises a gate electrode on the semiconductor layer. The gate electrode comprises a single-crystal semiconductor material. The structure further comprises a spacer structure including a first portion that overlaps with a side surface of the dielectric layer and a second portion that overlaps with a portion of the semiconductor substrate adjacent to the side surface of the dielectric layer.

Structures for a field-effect transistor that include a spacer structure

A transistor includes a semiconductor substrate, a first source/drain region and a second source/drain region in the semiconductor substrate with a channel region between the source/drain regions, and a gate over the channel region. In addition, the transistor includes a first phase transition material (PTM) region between the first source/drain region and the channel region, and a second PTM region between the second source/drain region and the channel region. The PTM regions provide the transistor with improved off-state current (I) without affecting the on-state current (I), and thus an improved I/Iratio. The transition threshold of PTM regions from dielectric to conductor can be customized based on, for example, PTM material type, doping therein, and/or strain therein.

Transistor with phase transition material region between channel region and each source/drain region

Methods of locally changing the BOX layer of a MOSFET device to a high-k layer to provide different Vts with one backside voltage and the resulting device are provided. Embodiments include providing a Si substrate having a BOX layer formed over the substrate and a SOI layer formed over the BOX layer; implanting a high current of dopants into at least one portion of the BOX layer; performing a high-temperature anneal of the BOX layer; forming first and second fully depleted silicon-on-insulator (FDSOI) transistors on the SOI layer, the first FDSOI transistors formed above either the BOX layer or the at least one portion of the BOX layer and the second FDSOI transistors formed above the at least one portion of the BOX layer; and applying a single voltage across a backside of the Si substrate.

FDSOI channel control by implanted high-k buried oxide

A semiconductor device includes a plurality of spaced apart fins, a dielectric material layer positioned between each of the plurality of spaced apart fins, and a common gate structure positioned above the dielectric material layer and extending across the fins. A continuous merged semiconductor material region is positioned on each of the fins and above the dielectric material layer, is laterally spaced apart from the common gate structure, extends between and physically contacts the fins, has a first sidewall surface that faces toward the common gate structure, and has a second sidewall surface that is opposite of the first sidewall surface and faces away from the common gate structure. A stress-inducing material is positioned in a space defined by at least the first sidewall surface, opposing sidewall surfaces of an adjacent pair of fins, and an upper surface of the dielectric material layer.

Three-dimensional transistor with improved channel mobility

FDSOI channel control by implanted high-K buried oxide

A method of forming a semiconductor device structure is disclosed including providing a first active region and a second active region in an upper surface portion of a substrate, the first and second active regions being laterally separated by at least one isolation structure, forming a first gate structure comprising a first gate dielectric and a first gate electrode material over the first active region, and a second gate structure comprising a second gate dielectric and a second gate electrode material over the second active region, wherein a thickness of the second gate dielectric is greater than the thickness of the first gate dielectric, and forming a first sidewall spacer structure to the first gate structure and a second sidewall spacer structure to the second gate structure, wherein a lateral thickness of the second sidewall spacer structure is greater than a lateral thickness of the first sidewall spacer structure.

Method of forming a semiconductor device structure using differing spacer widths and the resulting semiconductor device structure

A semiconductor device includes drain and source regions positioned in an active region of a transistor and a channel region positioned laterally between the drain and source regions that includes a semiconductor base material and a threshold voltage adjusting semiconductor material positioned on the semiconductor base material. A gate electrode structure is positioned on the threshold voltage adjusting semiconductor material, and a strain-inducing semiconductor alloy including a first semiconductor material and a second semiconductor material positioned above the first semiconductor material is embedded in the semiconductor base material of the active region. A crystalline buffer layer of a third semiconductor material surrounds the embedded strain-inducing semiconductor alloy, wherein an upper portion of the crystalline buffer layer laterally confines the channel region including the sidewalls of the threshold voltage adjusting semiconductor material and is positioned between the second semiconductor material and the threshold voltage adjusting semiconductor material.

Performance enhancement in transistors by providing an embedded strain-inducing semiconductor material on the basis of a seed layer

The present disclosure provides in one aspect for a semiconductor device structure which may be formed by providing source/drain regions within a semiconductor substrate in alignment with a gate structure formed over the semiconductor substrate, wherein the gate structure has a gate electrode structure, a first sidewall spacer and a second sidewall spacer, the first sidewall spacer covering sidewall surfaces of the gate electrode structure and the sidewall spacer being formed on the first sidewall spacer. Furthermore, forming the semiconductor device structure may include removing the second sidewall spacer so as to expose the first sidewall spacer, forming a third sidewall spacer on a portion of the first sidewall spacer such that the first sidewall spacer is partially exposed, and forming silicide regions in alignment with the third sidewall spacer in the source/drain regions.

Method of forming a semiconductor device structure and such a semiconductor device structure

Methods for forming a semiconductor device are provided. In one embodiment, a gate structure having a gate insulating layer and a gate electrode structure formed on the gate insulating layer is provided. The methods provide reducing a dimension of the gate electrode structure relative to the gate insulating layer along a direction extending in parallel to a direction connecting the source and drain. A semiconductor device structure having a gate structure including a gate insulating layer and a gate electrode structure formed above the gate insulating layer is provided, wherein a dimension of the gate electrode structure extending along a direction which is substantially parallel to a direction being oriented from source to drain is reduced relative to a dimension of the gate insulating layer. According to some examples, gate structures are provided having a gate silicon length which is decoupled from the channel width induced by the gate structure.

Contact geometry having a gate silicon length decoupled from a transistor length

The present disclosure provides a method of forming a semiconductor device and a semiconductor device. An SOI substrate portion having a semiconductor layer, a buried insulating material layer and a bulk substrate is provided, wherein the buried insulating material layer is interposed between the semiconductor layer and the bulk substrate. The SOI substrate portion is subsequently patterned so as to form a patterned bi-layer stack on the bulk substrate, which bi-layer stack comprises a patterned semiconductor layer and a patterned buried insulating material layer. The bi-layer stack is further enclosed with a further insulating material layer and an electrode material is formed on and around the further insulating material layer. Herein a gate electrode is formed by the bulk substrate and the electrode material such that the gate electrode substantially surrounds a channel portion formed by a portion of the patterned buried insulating material layer.

Methods of forming a complex GAA FET device at advanced technology nodes

Methods for fabricating an integrated circuit are provided herein. In an embodiment, a method for fabricating an integrated circuit includes forming a gate electrode structure overlying a semiconductor substrate. A first sacrificial oxide layer is formed overlying the semiconductor substrate and a first implant mask is patterned overlying the first sacrificial oxide layer to expose a portion of the first sacrificial oxide layer adjacent the gate electrode structure. Conductivity determining ions are implanted into the semiconductor substrate, through the first sacrificial oxide layer. The first implant mask and the first sacrificial oxide layer are removed after implanting the conductivity determining ions into the semiconductor substrate.

Methods for fabricating integrated circuits with semiconductor substrate protection

When forming transistors with deuterium enhanced gate dielectrics and strained channel regions, the manufacturing processes of strain-inducing dielectric material layers formed above the transistors may be employed to efficiently introduce and diffuse the deuterium to the gate dielectrics. The incorporation of deuterium into the strain-inducing dielectric material layers may be accomplished on the basis of a deposition process in which deuterium is present in the process environment during deposition. The process temperature of the deposition process may be chosen to perform&#x2014;potentially in combination with further subsequently performed process steps&#x2014;a sufficient diffusion of deuterium to the gate dielectrics.

Enhancing transistor performance and reliability by incorporating deuterium into a strained capping layer

The present disclosure provides, in various aspects of the present disclosure, a semiconductor device which includes a semiconductor stack disposed over a surface of a substrate and a gate structure partially formed over an upper surface and two opposing sidewall surfaces of the semiconductor stack, wherein the semiconductor stack includes an alternating arrangement of at least two layers formed by a first semiconductor material and a second semiconductor material which is different from the first semiconductor material.

Multi-gate FETs having corrugated semiconductor stacks and method of forming the same

A method to implant dopants onto fin-type field-effect-transistor (FINFET) fin surfaces with uniform concentration and depth levels of the dopants and the resulting device are disclosed. Embodiments include a method for pulsing a dopant perpendicular to an upper surface of a substrate, forming an implantation beam pulse; applying an electric or a magnetic field to the implantation beam pulse to effectuate a curvilinear trajectory path of the implantation beam pulse; and implanting the dopant onto a sidewall surface of a target FINFET fin on the upper surface of the substrate via the curvilinear trajectory path of the implantation beam pulse.

FINFET doping method with curvilnear trajectory implantation beam path

The present invention relates to a semiconductor structure comprising at least a first and a second three-dimensional transistor, wherein the first transistor and the second transistor are electrically connected in parallel to each other, and wherein each transistor comprises a source and a drain, wherein the source and/or drain of the first transistor is at least partially separated from, respectively, the source and/or drain of the second transistor. The invention further relates to a process for realizing such a semiconductor structure.

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Radeburg, Germany

Peter Javorka