Oak Technology, Inc.

Chrontel Inc.

Peter J Lim

Tat C Choi

The invention provides for an input/output circuit in a CMOS integrated circuit which can withstand pad voltages which are higher than the supply voltages for the integrated circuit. The input/output circuit has a pair of first polarity-type transistors which is connected in series between a first supply voltage terminal and the input/output pad, and a pair of second polarity-type transistors which is connected in series between a second supply voltage terminal and the pad. Responsive to a disable control signal, one of the first polarity-type and one of the second polarity-type transistors are turned off. Switch circuitry is connected between the pad and a gate of a second transistor of the second polarity-type transistor pair. The switch circuitry forms an open circuit when the pad voltage is in the range of the supply voltages of the input/output circuit, and forms a closed circuit to connect the gate to the pad when the pad voltage is outside the range of supply voltages so that no conducting path is created through the pair of second polarity-type transistors. This allows the pad to remain in a high impedance state even when the pad voltage is outside the range of supply voltages.

CMOS I/O circuit with high-voltage input tolerance

A comparator circuit providing for improved symmetry of operation. The circuit includes two delay paths to facilitate rising and falling input transitions. Such paths are made up of an equal number and type of current mirrors. The circuit also includes an input differential pair wherein both delay paths are coupled to a single transistor of the pair.

CMOS low-voltage comparator

A graphics subsystem converts a first graphics data stream for display on a computer monitor having a first refresh rate into a second graphics data stream for a television monitor having a second, slower refresh rate. The graphics subsystem has a first memory for storing one horizontal scan line of pixel data and a second memory for storing one half of a horizontal scan line of pixel data. Multiplexers direct data to a first summing circuit from an input port and from the first memory itself, so that a first horizontal line of input pixel data is initially stored in the first memory and a second horizontal line of input pixel data is combined with the first horizontal line of data by the first summing circuit, and the resulting combined pixel data is stored in back into the first memory. A controller sends the combined pixel data from the first memory to a second summing circuit while a next horizontal line of input pixel data is received. The second summing circuit combines that next horizontal line of input pixel data with data from the first memory so as to generate vertically averaged pixel data that is then stored in the second memory. The vertically averaged pixel data in the second memory is sent to an output port at a rate of no less than one half the rate at which pixel data is being received at the input port.

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San Jose, CA, United States of America

Peter J Lim