U.S. Philips Corporation

Peter H Kranen

Henricus G Maas

Johannes W Van Der Velden

Armand Pruijmboom

Marguerite M Van Iersel-Schiffmacher

Date J Noorlag

Johanna M Van Rooij-Mulder

Albertus T Van De Goor

Roland A Van Es

A method of manufacturing a semiconductor device whereby an spacer is formed from a second layer in a fully self-registering manner after a layer portion of a first layer has been formed. For this purpose, the second layer and a masking layer are provided in that order, which masking layer has a greater thickness next to the layer portion than above it. The portion of the second layer situated above the layer portion and the spacer to be formed is then exposed in that the masking layer is etched back over at least substantially its entire surface. A portion of the masking layer then remains next to the layer portion, which masking layer portion is sufficiently thick for adequately protecting the subjacent portion of the second layer against the treatment which is subsequently carried out and by which the etching resistance of at least the top layer of the exposed portion of the second layer is increased. The non-treated portion of the second layer is then selectively etched relatively to the treated portion in order to form the spacer.

Method of manufacturing a semiconductor device having a spacer

A device area (16) is defined in a semiconductor body (10) by forming at one major surface (12, 12a) of the body a step (11) having a side wall (11a) and top surface (11b) bounding the device area 16. A silicon layer (13) is deposited so as to cover the side wall (11a) and top surface (11b) of the step and an adjoining lower surface area (12c). Dopant impurities are introduced so that the side wall silicon region (13a) is shielded from the dopant impurities and the undoped side wall silicon region (13a) is later removed by selective etching. The silicon region (13c) on the lower surface area (12a) adjoining the step (11) is masked and the silicon region (13a) on the top surface (11b) at the step (11) removed to leave the doped silicon region (13c) on the one major surface (12a) for contacting a device region (29), for example the base region of a transistor, of the device area.

Method of manufacturing a semiconductor device

A semiconductor device comprising a first region, which is laterally bounded by a second region comprising a countersunk oxide layer and a highly doped polycrystalline silicon layer, which is disposed thereon and is covered by an oxide layer partly countersunk into it. The side edge of the polysilicon layer adjoins a contact zone, which is obtained by diffusion therefrom and is connected via a current path to a zone of a semiconductor circuit element. The upper side of the polysilicon layer is located at a higher level than that of the first region and the contact zone is connected to the said zone of the semiconductor circuit element via an intermediate region located in the first region below the second oxide layer and having a lower doping than the contact zone.

High efficiency, small geometry semiconductor devices

Growing community of inventors

Eindhoven, Netherlands

Peter H Kranen