Flip Chip Technologies, L.l.c.

Flipchip International LLC

Ppg Industries Ohio, Inc.

Optopac Co., Ltd.

Peter Elenius

Harry Hollack

Alan E Wang

Kevin C Olson

Michael E Johnson

Deok Hoon Kim

Thomas W Goodman

Hong Yang

Deok-Hoon Kim

Young Sang Cho

An electronic device package includes a substrate assembly, an electronic device disposed to face the substrate assembly, and a sealing ring or rings including a sealing layer and a bonding layer that is disposed between the substrate assembly and the electronic device, wherein the sealing ring(s) has a closed loop shape surrounding a sealing region of the electronic device, and the bonding layer is formed through a reaction of the sealing layer and sealing layer pad with a low-melting-point material layer whose melting point is lower than that of the sealing layer and sealing ring pad. The bonding layer is formed of an intermetallic compound of the sealing layer, sealing ring pad and low-melting-point material that melts at a temperature greater than the melting temperature of the low-melting-point material. The device package also includes electrical connections in the form of joints between the substrate assembly and electronic device.

Electronic device package and method for fabricating the same

A circuit board or each circuit board of a multi-layer circuit board includes an electrically conductive sheet coated with an insulating top layer covering one surface of the conductive sheet, an insulating bottom layer covering another surface of the conductive sheet and an insulating edge layer covering an edge of the conductive sheet. An insulating interlayer can be sandwiched between a pair of adjacent circuit boards of a multi-layer circuit board assembly. A landless through-hole or via can extend through one or more of the circuit boards for connecting electrical conductors on opposing surfaces thereof.

Method of forming a circuit board with improved via design

Single or multi-layer printed circuit board with improved via design

A wafer-level CSP () includes at least one die () from a wafer. The wafer-level CSP has a plurality of solder ball pads (), a solder ball () at each solder ball pad and a polymer collar () around each solder ball. A moat () is formed in the surface of a polymer layer () disposed on the wafer during manufacturing of the wafer-level CSP. A temporarily liquified residual () from the polymer collar, which occurs while the wafer is heated to the reflow temperature of the solder ball, flows from the polymer collar. The moat acts as a barrier to material flow, limiting the distance that the residual spreads while liquified. The residual from the polymer collar remains within a region () defined by the moat. A full-depth moat () extends completely through the polymer layer. Alternatively, a partial-depth moat (and) extends partially through the polymer layer. The abstract is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims pursuant to 37 C.F.R. &#xa7;1.72(b).

Wafer-level moat structures

A photomask () for producing partial-depth features (and) in a photo-imageable polymer layer () on a wafer of a chip scale package () using exposure tools capable of resolving sizes of a critical dimension or larger, has a plurality of chrome lines (). Each chrome line has a width () that is less than the critical dimension, and each chrome line of the plurality of chrome lines is spaced apart less than the critical dimension. The plurality of chrome lines produces a single partial-depth feature, such as a via, through part of a thickness of the polymer layer. Alternatively, the photomask has a plurality of chrome circles (), each chrome circle having a diameter less than the critical dimension and being spaced apart less than the critical dimension, which produces the partial-depth feature. The photomask may also have chrome of width greater than the critical dimension and spaced from other chrome by a distance greater than the critical dimension, which produces a full-depth feature through the entire thickness of the polymer film. The partial-depth feature and the full-depth feature are produced substantially simultaneously during a single series of photo-imaging steps. By preselecting a size, shape and distance between the chrome, the photomask is capable of inscribing discernable markings on the polymer layer, of changing the thickness of the polymer layer, and of changing an optical property of the surface of the polymer layer.

Forming partial-depth features in polymer film

A solder bar compatible with conventional flip chip technology fabrication methods for high power/high current applications includes first and second generally circular solder pads of diameter D formed upon a substrate and connected by a solder bar pad of width BW. The centers of the generally circular solder pads are spaced apart by distance BL (bar length). A mass of solder having volume VB is formed over the first and second generally circular solder pads and over the solder bar pad to form a dog-bone shaped solder bar. The solder bar reaches height Habove the centers of the first and second generally circular solder pads, and reaching height Habove the midpoint of the solder bar pad. The values for diameter D, bar length BL, bar width BW, and solder volume VB are selected in such manner that Hand Hare approximately equal. Conventional circular (as viewed from above) solder bumps can be formed upon the same substrate; in this case, heights Hand Hare made approximately equal to the height of the conventional solder bumps.

Solder bar for high power flip chips

A chip scale package design for a flip chip integrated circuit includes a redistribution metal layer upon the upper surface of a semiconductor wafer for simultaneously forming solder bump pads as well as the metal redistribution traces that electrically couple such solder bump pads with the conductive bond pads of the underlying integrated circuit. A patterned passivation layer is applied over the redistribution metal layer. Relatively large, ductile solder balls are placed on the solder bump pads for mounting the chip scale package to a circuit board or other substrate without the need for an underfill material. The back side of the semiconductor wafer can be protected by a coating for mechanical strength during handling. A method of forming such a chip scale package at the wafer processing level is also disclosed.

Method for forming chip scale package

A method of forming a polymer support ring, or collar, around the base of solder balls used to form solder joints includes forming patterned regions of uncured polymer material over each of the conductive solder bump pads on an IC package or other substrate to which the solder balls are to be attached. Preferably, the uncured polymer material is a no-flow underfill material that fluxes the solder bump pads. Pre-formed solder balls are then placed into the uncured polymer material onto their respective solder bump pads. A subsequent heating cycle raises the assembly to the reflow temperature of the solder balls, thereby attaching the solder balls to the underlying solder bump pads, and at least partially curing the polymer material to form a support collar at the base region of each attached solder ball.

Growing community of inventors

Scottsdale, AZ, United States of America

Peter Elenius