Commissariat &#xc0; L'&#xc9;nergie Atomique Et Aux &#xc9;nergies Alternatives

Stmicroelectronics S.a.

Commissariat a L'energie Atomique

Perrine Batude

Maud Vinet

Shay Reboh

Benoit Sklenard

Frederic Mazen

Claire Fenouillet-Beranger

Francois Andrieu

Laurent Brunet

Nicolas Posseme

Olivier Thomas

Hubert Bono

Laurent Clavelier

Yves Morand

Frank Fournel

Didier Lattard

Emmanuel Augendre

Sylvain Maitrejean

Thomas Ernst

Jean-Michel Hartmann

Frédéric Mazen

Benoit Mathieu

François Andrieu

Marie-Anne Jaud

Gilles Sicard

Christophe Licitra

Lina Kadura

Benoît Sklenard

Arnaud Pouydebasque

Fabien Deprat

Flavia Piegas Luce

Benoît Mathieu

Three-dimensional microelectronic circuit with optimised distribution of its digital and analogue functions

An image sensor including a plurality of pixels, each pixel including a photodetector coupled to a control circuit, the photodetector being formed inside and on top of a first semiconductor substrate, and the control circuit including at least one first MOS transistor formed inside and on top of a second semiconductor substrate arranged on the first substrate, the sensor being intended to be illuminated on the side of the surface of the first substrate opposite to the second substrate, the sensor further comprising a shield arranged between the first and second substrates and extending over substantially the entire surface of the sensor, said shield including at least one electrically-conductive layer.

Image sensor formed in sequential 3D technology

An optoelectronic device manufacturing method including the steps of: a) forming an active diode stack including first and second of opposite conductivity types; b) forming an integrated control circuit including a plurality of elementary control cells each including at least one MOS transistor; c) after steps a) and b), transferring the integrated control circuit onto the upper surface of the active diode stack; and d) after step c), forming trenches extending vertically through the integrated control circuit and emerging into or onto the first layer and delimiting a plurality of pixels each including a diode and an elementary control cell.

Method of manufacturing an optoelectronic device comprising a plurality of diodes

A method of manufacturing an optoelectronic device, including the steps of: a) providing an active diode stack comprising a first doped semiconductor layer of a first conductivity type and a second doped semiconductor layer of the first conductivity type, coating the upper surface of the first layer; b) arranging a third semiconductor layer on the upper surface of the active stack; c) after step b), forming at least one MOS transistor inside and on top of the third semiconductor layer; and d) after step b), before or after step c), forming trenches vertically extending from the upper surface of the third layer and emerging into or onto the upper surface of the first layer and delimiting a plurality of pixels, each including a diode and an elementary diode control cell.

Method of manufacturing an optoelectronic device comprising a plurality of diodes and an electronic circuit for controlling these diodes

A production of a device with superimposed levels of components including in this order providing on a given level Nprovided with one or more components produced at least partially in a first semiconductor layer: a stack including a second semiconductor layer capable of receiving at least one transistor channel of level N, above said given level N, the stack including a ground plane layer situated between the first and second semiconductor layers as well as an insulator layer separating the ground plane layer from the second semiconductor layer, one or more islands being defined in the second semiconductor layer. A gate is formed on at least one island. Distinct portions are etched in the second semiconductor ground plane layer. An isolation zone is formed around the island by the gate and the island.

3D circuit provided with mesa isolation for the ground plane zone

A method of production of a 3D microelectronic device includes assembling a structure comprising a lower level with a component partially formed in a first semiconductor layer with a support provided with a second semiconductor layer in which a transistor channel of an upper level is capable of being produced, the second semiconductor layer being capped with a dielectric material layer capable of forming a gate dielectric, forming a capping layer arranged on the dielectric material layer, and potentially capable of forming a lower gate portion of the transistor, and defining a gate dielectric zone and an active zone of said transistor by etching the dielectric material layer and the second semiconductor layer, the capping layer protecting said dielectric material layer during this etching.

Production of a 3D circuit with upper level transistor provided with a gate dielectric derived from a substrate transfer

An integrated circuit is provided with several superimposed levels of transistors, the circuit including an upper level provided with transistors having a rear gate electrode laid out on a first semiconducting layer, and a second semiconducting layer, a first transistor among the transistors of the upper level being provided with a contact pad traversing the second semiconducting layer, the contact pad being connected to a connection zone disposed between the first semiconducting layer and the second semiconducting layer, the first transistor being polarised by and connected to at least one power supply line disposed on a side of a front face of the second semiconducting layer that is opposite to the rear face.

3D circuit transistors with flipped gate

Method for producing a device provided with FinFET transistors, comprising the following steps:

Method for manufacturing pairs of CMOS transistors of the 'fin-FET' type at low temperatures

A method for producing a microelectronic device with one or more transistor(s) including forming a first gate on a region of a semiconductor layer, forming a first cavity in the semiconductor layer, the first cavity having a wall contiguous with the given region, filling the first cavity in such a way as to form a first semiconductor block wherein a source or drain region of the first transistor is capable of being produced, by epitaxial growth of a first semiconductor material in the first cavity, the growth being carried out such that a first zone of predetermined thickness of the layer of first semiconductor material lines the wall contiguous with the given region, epitaxial growth of a second zone made of a second semiconductor material on the first zone.

Transistor with controlled overlap of access regions

A method is provided for forming a transistor from a stack including the following successive layers: an electrically insulating layer, an active zone including at least one semiconductor layer, and a gate, sides of which are configured to be covered by at least one spacer, the method including: a phase of forming lateral cavities; and forming a raised drain and a raised source that fill the lateral cavities by growing the semiconductor layer via epitaxy, the forming of the lateral cavities includes, after a step of partially removing the semiconductor layer: forming a sacrificial layer, partially removing the sacrificial layer; forming spacers against the sides of the gate resting on a residual sacrificial layer; and totally removing the residual sacrificial layer in order to form the lateral cavities.

Method of manufacturing a dopant transistor located vertically on the gate

A method of fabrication of an integrated circuit is provided, including: providing a substrate including a first active layer and a first metallic level of interconnection arranged on top of the active layer and including first lines of interconnection separated by a first filling of sacrificial material; forming a superposition of an insulator layer and second lines of interconnection; providing access to the first filling through the insulator layer; filling the provided access with a second filling of sacrificial material; forming a second active layer on top of the second metallic level of interconnection; providing access to the second filling through the second active layer; and removing the first and the second fillings by a chemical etching through the provided access to the second filling.

Integrated circuit having a plurality of active layers and method of fabricating the same

Method of making a transistor, comprising the following steps:

Method of making a transistor having a source and a drain obtained by recrystallization of semiconductor

Method including the steps consisting in:

Method for doping source and drain regions of a transistor by means of selective amorphisation

This method includes the following steps: a) providing a first structure successively including a substrate, an electronic device, a dielectric layer, and a first semiconductor layer; b) providing a second structure successively including a substrate, an active layer, a dielectric layer, and a second semiconductor layer, the active layer being designed to form an electronic device; c) bonding the first and second structures by direct bonding between the first and second semiconductor layers so as to form a bonding interface; d) removing the substrate of the second structure so as to expose the active layer; e) introducing dopants into the first and second semiconductor layers so as to form a ground plane.

Fabrication method of a stack of electronic devices

A method for producing a microelectronic device is provided, including forming on an insulating layer of a semi-conductor on insulator type substrate, a first semi-conductor block covered with a first strain zone configured to induce a compressive strain in the first block and a second semi-conductor block covered with a second strain zone configured to induce a tensile strain in the second block, the first block and the second block each being formed of a lower region based on amorphous semi-conductor material, covered with an upper region of crystalline semi-conductor material in contact with one of the strain zones; and recrystallizing the lower region of the first and second blocks while using the upper region of crystalline material as starting zone for a recrystallization front.

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Dijon, France

Perrine Batude