Micron Technology Incorporated

Intel Corporation

Pengyuan Zheng

Yongjun Jeff Hu

Andrea Redaelli

David Ross Economy

Robert K Grubbs

Kent H Zhuang

Rajasekhar Venigalla

Andrea Gotti

Hongqi Li

Kevin Lee Baker

Lei Wei

Efe Sinan Ege

Adam Thomas Barton

Yao Jin

Lorenzo Fratin

Dale Collins

Stephen W Russell

Enrico Varesi

Jaydeb Goswami

Yiping Wang

Russell A Benson

Ying Rui

Caizhi Xu

Yongiun J Hu

Methods, systems, and devices related to a memory device with a thermal barrier are described. The thermal barrier (e.g., a low density thermal barrier) may be positioned between an access line (e.g., a digit line or a word line) and a cell component. The thermal barrier may be formed on the surface of a barrier material by applying a plasma treatment to the barrier material. The thermal barrier may have a lower density than the barrier material and may be configured to thermally insulate the cell component from thermal energy generated in the memory device, among other benefits.

Memory device with low density thermal barrier

A variety of applications can include apparatus having a memory device structured with an array of memory cells and a complementary metal-oxide-semiconductor (CMOS) device coupled to the array. The CMOS device can include a gate electrode on and contacting the polysilicon gates of a p-channel metal-oxide-semiconductor (PMOS) transistor and a n-channel metal-oxide-semiconductor (NMOS) transistor of the CMOS device, where the gate electrode is a multi-metal stack. The multi-metal stack of the gate electrode can be two levels of different metal compositions.

Metal gate stacks for CMOS scaling

A memory system may include separate amounts or types of resistive material that may be deposited over memory cells and conductive vias using separate resistive layers in the access lines. A first resistive material layer may be deposited over the memory cells prior to performing an array termination etch used to deposit the conductive via. The array termination etch may remove the first resistive material over the portion of the array used to deposit the conductive via. A second resistive material layer may be deposited after the etch has occurred and the conductive via has been formed. The second resistive material layer may be deposited over the conductive via.

Memory with optimized resistive layers

Methods, systems, and devices for a memory device with a high resistivity thermal barrier are described. In some examples a barrier material may be positioned over a memory cell region, an oxide region, and/or a through-silicon via (TSV). The barrier may include a first region above the memory cell region and a second region above the TSV. A process, such as a plasma treatment, may be applied to the barrier, which may result in the first and second regions having different thermal resistivities (e.g., different densities). Accordingly, due to the different thermal resistivities, the memory cells may be thermally insulated from thermal energy generated in the memory device.

Memory device with high resistivity thermal barrier

Methods, systems, and devices for composite electrode material chemistry are described. A memory device may include an access line, a storage element comprising chalcogenide, and an electrode coupled with the memory element and the access line. The electrode may be made of a composition of a first material doped with a second material. The second material may include a tantalum-carbon compound. In some cases, the second may be operable to be chemically inert with the storage element. The second material may include a thermally stable electrical resistivity and a lower resistance to signals communicated between the access line and the storage element across a range of operating temperatures of the storage element as compared with a resistance of the first material.

Composite electrode material chemistry

Memory devices having electrode structures that increase in resistivity with thermal cycling, and associated systems and methods, are disclosed herein. In some embodiments, a memory device includes a memory element and an electrode structure electrically coupled to the memory element. The electrode structure can include a material comprising a composition of tungsten, silicon, and germanium.

WSiGe electrode structures for memory devices, and associated devices and systems

Methods, systems, and devices for fabrication of memory cells are described. An electrode layer may have an initial thickness variation after being formed. The electrode layer may be smoothened prior to forming additional layers of a memory cell, thus decreasing the thickness variation. The subsequent layer fabricated may have a thickness variation that may be dependent on the thickness variation of the electrode layer. By decreasing the thickness variation of the electrode layer prior to forming the subsequent layer, the subsequent layer may also have a decreased thickness variation. The decreased thickness variation of the subsequent layer may impact the electrical behavior of memory cells formed from the subsequent layer. In some cases, the decreased thickness variation of the subsequent layer may allow for more predictable voltage thresholds for such memory cells, thus increasing the read windows for the memory cells.

Fabrication of electrodes for memory cells

A memory cell can include a phase change material layer and a first electrode layer adjacent to the phase change material layer and having a phase change material layer side oriented toward the phase change material layer and a bit line side opposite the phase change material layer side. A carbon nitride layer can be on the bit line side surface of the first electrode layer. In some examples, a nonconductive separator material can have a word line end and a bit line end, and can have a portion contacting the phase change material layer. The bit line end surface of the nonconductive separator material can be at least partially free of contact with the carbon nitride layer.

Memory cells

Systems, apparatuses, and methods related to atom implantation for reduction of compressive stress are described. An example method may include patterning a working surface of a semiconductor, the working surface having a hard mask material formed over a dielectric material and forming a material having a lower refractive index (RI), relative to a RI of the hard mask material, over the hard mask material. The method may further include implanting atoms through the lower RI material and into the hard mask material to reduce the compressive stress in the hard mask material.

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Boise, ID, United States of America

Pengyuan Zheng