Applied Materials, Inc.

Peng Suo

Arvind Sundarrajan

Guan Huei See

Yu Gu

Ying W Wang

Chang Bum Yong

Prayudi Lianto

The present disclosure relates to through-via structures with dielectric shielding of interconnections for advanced wafer level semiconductor packaging. The methods described herein enable the formation of high thickness dielectric shielding layers within low aspect ratio through-via structures, thus facilitating thin and small-form-factor package structures having high I/O density with improved bandwidth and power.

Methods of TSV formation for advanced packaging

A method of forming a magnetic core on a substrate having a stacked inductor coil includes etching a plurality of polymer layers to form at least one feature through the plurality of polymer layers, wherein the at least one feature is disposed within a central region of a stacked inductor coil formed on the substrate; and depositing a magnetic material within the at least one feature.

Semiconductor substrate having magnetic core inductor

Methods of forming through-silicon vias in substrates for advanced packaging

Method of forming a magnetic core on a substrate

A method of processing a substrate includes depositing a layer of uncured polymer material atop a substrate to cover an exposed conductive layer on the substrate, exposing at least one area of the layer using a photolithography process, developing the layer in the photolithography process to remove a first portion of uncured polymer material from the at least one area, etching the layer with a dry etch process to remove a second portion of uncured polymer material from the at least one area to expose a top surface of the conductive layer and form a via in the layer, and curing the layer to form a cured polymer material.

Methods for forming vias in polymer layers

Methods of processing a substrate include: providing a substrate with a first polymer dielectric layer; forming a first RDL on the first polymer dielectric layer; constructing a 3D MIM capacitive stack on the first RDL in at least one opening in a top surface of a second polymer dielectric layer, the 3D MIM capacitive stack having a top electrode, a bottom electrode, and a capacitive dielectric layer interposed between the top electrode and the bottom electrode; depositing a dielectric layer on the 3D MIM capacitive stack and on the second polymer dielectric layer; and removing a portion of the dielectric layer to expose at least a portion of the top electrode at a bottom of at least one opening of the 3D MIM capacitive stack and to expose at least a portion of the metal layer at a bottom of at least one opening of the second polymer dielectric layer.

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Singapore, Singapore

Peng Suo