Taiwan Semiconductor Manufacturing Comp. Ltd.

Other

Peng-Fu Hsu

Hun-Jan Tao

Kuo-Tai Huang

Yong-Tian Hou

Baw-Ching Perng

Jin Ying

Jyu-Horng Shieh

Kang-Cheng Lin

Ju-Wang Hsu

Fong-Yu Yen

Huan-Just Lin

Cheng-Lung Hung

Yi-Nien Su

Tze-Liang Lee

Ming-Huan Tsai

Yuan-Hung Chiu

Yi-Shien Mor

Chun-Li Chou

Vencent Chang

Jang-Shiang Tsai

Ying Jin

Wen-Chih Chiou

Carlos H Diaz

Chih-Wei Chang

Yung-Cheng Lu

Chung-Chi Ko

Ming-Hsing Tsai

Chien-Hao Chen

Chun-Hsien Huang

Chia-Jen Chen

Liang-Gi Yao

Shiang-Bau Wang

Kuang-Hsin Chen

Chen-Yuan Kao

Ken-Yu Chang

Yun Chi

Bor-Wen Chan

Hung-Wei Chen

Chun-I Tsai

Min-Hsiu Hung

Fang-Cheng Chen

Chia-Han Lai

Huan-Tsung Huang

Chih-Cheng Wang

Mong Song Liang

Donald Y Chao

Hsun-Chih Tsao

Yi-Chen Huang

Di-Hong Lee

Chuan-Ping Hou

Yuri Masuoka

Jhi-Cherng Lu

Mei-Hui Sung

Ssu-Yi Li

Jun-Lung Huang

Arthur Carty

Hsin-Ching Shih

Chao-Shiuan Liu

Tsung-Wu Lin

Lawrance Hsu

Yu-Syuan Cai

Yue-Ho Hsieh

Shih-Yi Hsiao

Yaun-Hung Chiu

In some implementations, one or more semiconductor processing tools may form a metal cap on a metal gate. The one or more semiconductor processing tools may form one or more dielectric layers on the metal cap. The one or more semiconductor processing tools may form a recess to the metal cap within the one or more dielectric layers. The one or more semiconductor processing tools may perform a bottom-up deposition of metal material on the metal cap to form a metal plug within the recess and directly on the metal cap.

Interconnect structures including a fin structure and a metal cap

The present disclosure provides a method of fabricating a semiconductor device. The method includes providing a semiconductor substrate having a first region and a second region, forming a high-k dielectric layer over the semiconductor substrate, forming a capping layer over the high-k dielectric layer in the first region, forming a first metal layer over capping layer in the first region and over the high-k dielectric in the second region, thereafter, forming a first gate stack in the first region and a second gate stack in the second region, protecting the first metal layer in the first gate stack while performing a treatment process on the first metal layer in the second gate stack, and forming a second metal layer over the first metal layer in the first gate stack and over the treated first metal layer in the second gate stack.

Method of fabricating dual high-k metal gates for MOS devices

Method of fabricating dual high-k metal gate for MOS devices

A semiconductor structure and methods for forming the same are provided. The semiconductor structure includes a first MOS device of a first conductivity type and a second MOS device of a second conductivity type opposite the first conductivity type. The first MOS device includes a first gate dielectric on a semiconductor substrate; a first metal-containing gate electrode layer over the first gate dielectric; and a silicide layer over the first metal-containing gate electrode layer. The second MOS device includes a second gate dielectric on the semiconductor substrate; a second metal-containing gate electrode layer over the second gate dielectric; and a contact etch stop layer having a portion over the second metal-containing gate electrode layer, wherein a region between the portion of the contact etch stop layer and the second metal-containing gate electrode layer is substantially free from silicon.

CMOS dual metal gate semiconductor device

A semiconductor structure includes a first MOS device including a first gate, and a second MOS device including a second gate. The first gate includes a first high-k dielectric over a semiconductor substrate; a second high-k dielectric over the first high-k dielectric; a first metal layer over the second high-k dielectric, wherein the first metal layer dominates a work-function of the first MOS device; and a second metal layer over the first metal layer. The second gate includes a third high-k dielectric over the semiconductor substrate, wherein the first and the third high-k dielectrics are formed of same materials, and have substantially a same thickness; a third metal layer over the third high-k dielectric, wherein the third metal layer and the second metal layer are formed of same materials, and have substantially a same thickness; and a fourth metal layer over the third metal layer.

Hybrid process for forming metal gates of MOS devices

A semiconductor device is disclosed that includes: a substrate; a first dielectric layer formed over the substrate and formed of a first high-k material, the first high-k material selected from the group consisting of HfO, HfSiO, HfSiON, HfTaO, HfTiO, HfTiTaO, HfAlON, and HfZrO; a second dielectric layer formed over the first dielectric layer and formed of a second high-k material, the second high-k material being different than the first high-k material and selected from the group consisting of HfO, HfSiO, HfSiON, HfTaO, HfTiO, HfTiTaO, HfAlON, and HfZrO; and a metal gate formed over the second dielectric layer. The first dielectric layer includes ions selected from the group consisting of N, O, and Si.

Semiconductor devices and methods with bilayer dielectrics

The present disclosure provides a method of fabricating a semiconductor device. The method includes providing a semiconductor substrate having a first active region and a second active region, providing a semiconductor substrate having a first region and a second region, forming a high-k dielectric layer over the semiconductor substrate, forming a first capping layer and a second capping layer over the high-k dielectric layer, the first capping layer overlying the first region and the second capping layer overlying the second region, forming a layer containing silicon (Si) over the first and second capping layers, forming a metal layer over the layer containing Si, and forming a first gate stack over the first region and a second gate stack over the second active region. The first gate stack includes the high-k dielectric layer, the first capping layer, the layer containing Si, and the metal layer and the second gate stack includes the high-k dielectric layer, the second capping layer, the layer containing Si, and the metal layer.

Method to improve dielectric quality in high-k metal gate technology

A method is provided that allows for maintaining a desired equivalent oxide thickness (EOT) by reducing the thickness of an interfacial layer in a gate structure. An interfacial layer is formed on a substrate, a gate dielectric layer such as, a high-k gate dielectric, is formed on the interfacial layer. A gettering layer is formed on the substrate overlying the interfacial layer. The gettering layer may function to getter oxygen from the interfacial layer such that the interfacial layer thickness is decreased and/or restricted from growth.

Semiconductor device gate structure including a gettering layer

Semiconductor devices with dual-metal gate structures and fabrication methods thereof. A semiconductor substrate with a first doped region and a second doped region separated by an insulation layer is provided. A first metal gate stack is formed on the first doped region, and a second metal gate stack is formed on the second doped region. A sealing layer is disposed on sidewalls of the first gate stack and the second gate stack. The first metal gate stack comprises an interfacial layer, a high-k dielectric layer on the interfacial layer, a first metal layer on the high-k dielectric layer, a metal insertion layer on the first metal layer, a second metal layer on the metal insertion layer, and a polysilicon layer on the second metal layer. The second metal gate stack comprises an interfacial layer, a high-k dielectric layer on the interfacial layer, a second metal layer on the high-k dielectric layer, and a polysilicon layer on the second metal layer.

Semiconductor devices with dual-metal gate structures and fabrication methods thereof

A method of forming a semiconductor structure includes providing a semiconductor substrate, performing a hydrogen annealing to the semiconductor substrate, forming a base oxide layer after the step of hydrogen annealing, and forming a high-k dielectric layer on the base oxide layer.

Base oxide engineering for high-K gate stacks

Methods and structures for forming a contact hole structure are disclosed. These methods first form a substantially silicon-free material layer over a substrate. A material layer is formed over the substantially silicon-free material layer. A contact hole is formed within the substantially silicon-free material layer and the material layer without substantially damaging the substrate. In addition, a conductive layer is formed in the contact hole so as to form a contact structure.

Contact hole structures and contact structures and fabrication methods thereof

Hybrid process for forming metal gates

A semiconductor structure includes a substrate, a gate stack on the substrate, a source/drain region adjacent the gate stack, a source/drain silicide region on the source/drain region, a protection layer on the source/drain silicide region, wherein a region over the gate stack is substantially free from the protection layer, and a contact etch stop layer (CESL) having a stress over the protection layer and extending over the gate stack.

MOS devices with continuous contact etch stop layer

A fin-FET device and a method for fabrication thereof both employ a bulk semiconductor substrate. A fin and an adjoining trough are formed within the bulk semiconductor substrate. The trough is partially backfilled with a deposited dielectric layer to form an exposed fin region and an unexposed fin region. A gate dielectric layer is formed upon the exposed fin region and a gate electrode is formed upon the gate dielectric layer. By employing a bulk semiconductor substrate the fin-FET device is fabricated cost effectively.

FIN-FET device structure formed employing bulk semiconductor substrate

Growing community of inventors

Hsinchu, Taiwan

Peng-Fu Hsu