Micron Technology Incorporated

Peng Fei

Kishore Kumar Muchherla

Harish Reddy Singidi

Jung Sheng Hoei

Michael G Miller

Renato C Padilla

Gary F Besinga

Gianni Stephen Alsasua

Roland J Awusie

Naveen Bolisetty

Shakeel Isamohiuddin Bukhari

Yiran Liu

Dengfeng Ruan

A method for reducing active idle power is a memory device includes incrementing, by a first processing device, a first counter when no read or write requests are received from a host system within a first predetermined period of time, and in response to determining that the first counter has reached a first predetermined threshold value, transitioning to a sleep mode. The method also includes incrementing, by a second processing device, a second counter when no read or write requests are received from the host system within a second predetermined period of time, and in response to determining that the second counter has reached a second predetermined threshold value, transitioning to the sleep mode.

Media scan method to reduce active idle power of memory devices

A method is described, which includes receiving, by a memory subsystem controller from a host system, a host read memory command that references a set of logical block addresses associated with a set of transfer units of a memory device. The controller converts the set of logical block addresses to a set of physical block addresses for the set of transfer units; generates a set of device read memory commands based on the physical block addresses, wherein each device read memory command references at least one physical block address; and generates a first aggregated device read memory command based on a first device read memory command and a second read memory command in response to determining that the first device read memory command is associated with the second device read memory command. The controller thereafter transmits the first aggregated device read memory command to the memory device.

Memory command aggregation to improve sequential memory command performance

Several embodiments of memory devices and systems with read level calibration are disclosed herein. In one embodiment, a memory device includes a controller operably coupled to a main memory having at least one memory region and calibration circuitry. The calibration circuitry is operably coupled to the at least one memory region and is configured to determine a read level offset value corresponding to a read level signal of the at least one memory region. In some embodiments, the calibration circuitry is configured to obtain the read level offset value internal to the main memory. The calibration circuitry is further configured to output the read level offset value to the controller.

Memory devices with read level calibration

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Shanghai, China

Peng Fei