Taiwan Semiconductor Manufacturing Comp. Ltd.

Peng-Chung Jangjian

Chun-Wen Hsiao

Chu-An Lee

Kao-Feng Liao

Teng-Chun Tsai

Kei-Wei Chen

Liang-Guang Chen

Huang-Lin Chao

Chen-Hao Wu

Hsin-Ying Ho

Ting-Hsun Chang

Sheng-Chao Chuang

Chun-Chieh Lin

Chun-Wei Hsu

Chih Hung Chen

Chi-Jen Liu

Hui-Chi Huang

Fu-Ming Huang

Ji Cui

Ji James Cui

Hui-chi Huang

Michael Yen

Li-Chieh Wu

Tang-Kuei Chang

Wei-Wei Liang

Chih-chieh Chang

Fu-ming Huang

A slurry composition, a polishing method and an integrated circuit are provided. The slurry composition includes a slurry and at least one cationic surfactant having at least one nitrogen atom in the molecule. The slurry includes at least one liquid carrier, at least one abrasive and at least one pH adjusting agent, and has a pH of less than 7.0. The polishing method includes using the slurry composition with the cationic surfactant to polish a conductive layer. The integrated circuit comprises a block layer comprising the cationic surfactant between a sidewall of the conductive plug and an interlayer dielectric layer.

Composition and method for polishing and integrated circuit

A slurry composition, a polishing method and an integrated circuit are provided. The slurry composition includes a slurry and at least one rheology modifier. The slurry includes at least one liquid carrier, at least one abrasives and at least one oxidizer. The rheology modifier is dispensed in the slurry. The polishing method includes using the slurry composition with the rheology modifier to polish a conductive layer.

Slurry composition and method for polishing and integrated circuit

A chemical mechanical planarization (CMP) tool includes a platen and a polishing pad attached to the platen, where a first surface of the polishing pad facing away from the platen includes a first polishing zone and a second polishing zone, where the first polishing zone is a circular region at a center of the first surface of the polishing pad, and the second polishing zone is an annular region around the first polishing zone, where the first polishing zone and the second polishing zone have different surface properties.

Chemical mechanical planarization tool

A semiconductor device structure is provided. The semiconductor device structure includes a first fin, a second fin and a third fin therebetween. A first insulating structure includes a first insulating layer formed between the first and third fins, a capping structure covering the first insulating layer, a first insulating liner covering sidewall surfaces of the first insulating layer and the capping structure and a bottom surface of the first insulating layer, and a second insulating liner formed between the first insulating liner and the first fin and between the first insulating liner and the third fin. The second insulating structure includes a second insulating layer formed between the second fin and the third fin and a third insulating liner formed between the second insulating layer and the second fin and between the second insulating layer and the third fin.

Fin isolation structure for FinFET and method of forming the same

A semiconductor device structure is provided. The semiconductor device structure includes a substrate having adjacent first and second fins protruding from the substrate. A first gate structure and a second gate structure are across the first and second fins, respectively. An insulating structure is formed between the first gate structure and the second gate structure and includes a first insulating layer separating the first fin from the second fin, a capping structure formed in the first insulating layer, and a second insulating layer covered by the first insulating layer and the capping structure.

A device includes a semiconductor fin protruding from a substrate, a first gate stack over the semiconductor fin and a second gate stack over the semiconductor fin, a first source/drain region in the semiconductor fin adjacent the first gate stack and a second source/drain region in the semiconductor fin adjacent the second gate stack, a first layer of a first dielectric material on the first gate stack and a second layer of the first dielectric material on the second gate stack, a first source/drain contact on the first source/drain region and adjacent the first gate stack, a first layer of a second dielectric material on a top surface of the first source/drain contact, and a second source/drain contact on the second source/drain region and adjacent the second gate stack, wherein the top surface of the second source/drain contact is free of the second dielectric material.

FinFET contacts and method forming same

A semiconductor device structure is provided. The semiconductor device structure includes a substrate having adjacent first and second fins protruding from the substrate. The semiconductor device structure also includes an insulating structure that includes a first insulating layer formed between and separating from the first fin and the second fin, a second insulating layer embedded in the first insulating layer, a first capping layer formed in the first insulating layer to cover a top surface of the second insulating layer, and a second capping layer in the first capping layer.

A semiconductor device structure is provided. The semiconductor device structure includes a substrate having adjacent first and second fins protruding from the substrate, an isolation feature between and adjacent to the first fin and the second fin, and a fin isolation structure between the first fin and the second fin. The fin isolation structure includes a first insulating layer partially embedded in the isolation feature, a second insulating layer having sidewall surfaces and a bottom surface that are covered by the first insulating layer, a first capping layer covering the second insulating layer and having sidewall surfaces that are covered by the first insulating layer, and a second capping layer having sidewall surfaces and a bottom surface that are covered by the first capping layer.

The present disclosure provides a chemical mechanical polishing (CMP) system. The CMP system includes a pad designed for wafer polishing, a motor driver coupled with the pad and designed to drive the pad during the wafer polishing, and a controller coupled with the motor driver and designed to control the motor driver. The CMP system further includes an in-situ rate monitor designed to collect polishing data from a wafer on the pad, determine CMP endpoint based on a life stage of the pad, and provide the CMP endpoint to the controller.

Adaptive endpoint method for pad life effect on chemical mechanical polishing

The present disclosure provides a semiconductor manufacturing method. The method includes defining a plurality of time regions of pad life for a polishing pad in a chemical mechanical polishing (CMP) system; assigning a ladder coefficient to the polishing pad according to the plurality of time regions of pad life; defining a plurality of endpoint windows to the plurality of time regions, respectively, according to pad life effect; applying a CMP process to a wafer positioned on the polishing pad; determining a time region of a polishing signal of the wafer based on the ladder coefficient; associating one of the endpoint windows to the polishing signal according to the time region; and ending the CMP process at an endpoint determined by the endpoint window.

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Hsinchu, Taiwan

Peng-Chung Jangjian