Qualcomm Incorporated

Other

Peijie Feng

Stanley Seungchul Song

Junjing Bao

Kern Rim

Ye Lu

Chenjie Tang

Jun Yuan

Giridhar Nallapati

Da Yang

Seung Hyuk Kang

Jonghae Kim

Periannan Chidambaram

Venugopal Boynapalli

Hyeokjin Lim

Foua Vang

Deepak Sharma

Bharani Chava

Hyunwoo Park

A multi-gate HEMT includes at least two gates, with at least one recessed the same depth or at a deeper depth in a barrier layer than at least one other gate. Recessing a gate decreases the thickness of the barrier layer beneath the gate, reducing a density of high mobility carriers in a two-dimensional electron gas layer (2DEG) conductive channel formed at the heterojunction of a barrier layer and a buffer layer below the recessed gate. The recessed gate can increase gate control of the 2DEG conductive channel. The multi-gate HEMT has at least one gate recessed the same depth or a deeper depth into the buffer layer than another gate, which forms at least two different turn-on voltages for different gates. This can achieve improvement of transconductance linearity and a positive shift of the threshold voltage.

Multi-gate high electron mobility transistors (HEMTs) employing tuned recess depth gates for improved device linearity

Gate-all-around (GAA) transistors with shallow source/drain regions and methods of fabricating the same provide a GAA transistor that includes one or more channels positioned between a source region and a drain region. The one or more channels, which may be nanowire, nanosheet, or nanoslab semiconductors, are surrounded along a longitudinal axis by gate material. At a first end of the channel is a source region and at an opposite end of the channel is a drain region. To reduce parasitic capacitance between a bottom gate and the source and drain regions, a filler material is provided adjacent the bottom gate, and the source and drain regions are grown on top of the filler material. In this fashion, the bottom gate does not abut the source region or the drain region, reducing geometries which would contribute to parasitic capacitance.

Gate-all-around (GAA) transistors with shallow source/drain regions and methods of fabricating the same

An integrated device that includes a substrate, a first transistor, and a second transistor. The second transistor is configured to be coupled to the first transistor. The first transistor is configured to operate as a N-type channel metal oxide semiconductor transistor (NMOS) transistor. The first transistor includes a dielectric layer disposed over the substrate; a first source disposed over the dielectric layer; a first drain disposed over the dielectric layer; a first plurality of channels coupled to the first source and the first drain; and a first gate surrounding the plurality of channels. The second transistor is configured to operate as a P-type channel metal oxide semiconductor transistor (PMOS). The second transistor includes the dielectric layer; a second source disposed over the dielectric layer; a second drain disposed over the dielectric layer; a second plurality of channels coupled to the second source and the second drain; and a second gate.

Integrated device comprising a CMOS structure comprising well-less transistors

Field-effect transistor (FET) circuits employing topside and backside contacts for topside and backside routing of FET power and logic signals. A FET circuit is provided that includes a FET that includes a conduction channel, a source, a drain, and a gate. The FET circuit also includes a topside metal contact electrically coupled with at least one of the source, drain, and gate of the FET. The FET circuit also includes a backside metal contact electrically coupled with at least one of the source, drain, and gate of the FET. The FET circuit also includes topside and backside metal lines electrically coupled to the respective topside and backside metal contacts to provide power and signal routing to the FET. A complementary metal oxide semiconductor (CMOS) circuit is also provided that includes a PFET and NFET that each includes a topside and backside contact for power and signal routing.

Field-effect transistors (FET) circuits employing topside and backside contacts for topside and backside routing of FET power and logic signals, and related complementary metal oxide semiconductor (CMOS) circuits

An integrated device that includes a substrate and a first transistor formed over the substrate. The first transistor includes a first source disposed over the substrate, a first drain disposed over the substrate, a first plurality of channels coupled to the first source and the first drain, where the first plurality of channels is located between the first source and the first drain; at least one inner spacer located between two adjacent channels from the first plurality of channels; at least two voids located between the two adjacent channels; and a first gate surrounding the first plurality of channels.

Field effect transistor (FET) comprising inner spacers and voids between channels

Disclosed are optimized contract structures and fabrication techniques thereof. At least one aspect includes a semiconductor die. The semiconductor die includes a substrate and a contact disposed within the substrate. The contact includes a first portion with a first vertical cross-section having a first cross-sectional area. The first vertical cross-section has a first width and a first height. The contact also includes a second portion with a second vertical cross-section having a second cross-sectional area less than the first cross-sectional area. The second vertical cross-section includes a lower portion having the first width and a second height less than the first height, and an upper portion disposed above the lower portion and having a second width less than the first width and having a third height less than the first height.

Optimized contact structure

Certain aspects of the present disclosure relate to a semiconductor device (e.g., a gate-all-around (GAA) semiconductor device) comprising at least one superlattice fin. One example superlattice fin includes a first plurality of nanosheets composed of a first semiconductor material and a second plurality of nanosheets composed of a second semiconductor material, the second semiconductor material being different from the first semiconductor material, wherein a width of a first nanosheet in the first plurality of nanosheets differs from a width of a second nanosheet in the second plurality of nanosheets, the second nanosheet being adjacent to the first nanosheet.

Semiconductor device with superlattice fin

Gate-all-around (GAA) transistors with an additional bottom channel for reduced parasitic capacitance and methods of fabricating the same include one or more channels positioned between a source region and a drain region. The one or more channels, which may be nanowire or nanoslab semiconductors, are surrounded by gate material. The GAA transistor further includes an additional semiconductor channel between a bottom section of a gate material and a silicon on insulator (SOI) substrate in a GAA transistor. This additional channel, sometimes referred to as a bottom channel, may be thinner than other channels in the GAA transistor and may have a thickness less than its length.

Gate-all-around (GAA) transistors with additional bottom channel for reduced parasitic capacitance and methods of fabrication

Certain aspects of the present disclosure generally relate to a gate-all-around (GAA) semiconductor device. The GAA semiconductor device generally includes a substrate, a first nanosheet stack structure, a second nanosheet stack structure, the first and second nanosheet stack structures being disposed above a horizontal plane of the substrate and each comprising one or more nanosheet structures, and a dielectric structure disposed between the first nanosheet stack structure and the second nanosheet stack structure.

Gate-all-around devices with reduced parasitic capacitance

Cell circuits having a diffusion break with avoided or reduced adjacent semiconductor channel strain relaxation and related methods are disclosed. In one aspect, a cell circuit includes a substrate of semiconductor material and a semiconductor channel structure(s) of a second semiconductor material disposed on the substrate. The semiconductor material applies a stress to the formed semiconductor channel structure(s) to induce a strain in the semiconductor channel structure(s) for increasing carrier mobility. A diffusion break comprising a dielectric material extends through a surrounding structure of an interlayer dielectric, and the semiconductor channel structure(s) and at least a portion of the substrate. The relaxation of strain in areas of the semiconductor channel structure(s) adjacent to the diffusion break is reduced or avoided, because the semiconductor channel structure(s) is constrained by the surrounding structure.

Circuits having a diffusion break with avoided or reduced adjacent semiconductor channel strain relaxation, and related methods

A capacitor includes first conductive fingers interdigitated with second conductive fingers at an Mx interconnect level, and third conductive fingers interdigitated with fourth conductive fingers at an Mx-1 interconnect level. The third conductive fingers are offset from the first conductive fingers. The second conductive fingers are offset from the fourth conductive fingers. The capacitor further includes fifth conductive fingers interdigitated with sixth conductive fingers at an Mx-2 interconnect level. The fifth conductive fingers are offset from the third conductive fingers. The sixth conductive fingers are offset from the fourth conductive fingers. The capacitor further includes seventh conductive fingers interdigitated with eighth conductive fingers at an Mx-3 interconnect level. The seventh conductive fingers are offset from the fifth conductive fingers. The eighth conductive fingers are offset from the sixth conductive fingers. A first set of vias electrically couples the first conductive fingers to the fifth conductive fingers.

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San Diego, CA, United States of America

Peijie Feng