Taiwan Semiconductor Manufacturing Comp. Ltd.

Tsinghua University

Pei-Yuan Li

Wei-Cheng Wu

Wei Min Chan

Kao-Cheng Lin

Chien-Chen Lin

Yen-Huei Chen

Chih-Cheng Yu

Yung-Ning Tu

Shang Lin Wu

Chien Hui Huang

Meng-Fan Chang

Chia-Che Chung

Tsung-Hsien Huang

Yen Lin Chung

Chia-Chi Hung

Hsiang-Yun Lin

A memory device is provided which includes a first memory cell including a first transistor and a second transistor coupled to the first transistor in parallel. Gates of the first transistor and the second transistor are coupled to each other, and the gates of the first transistor and the second transistor pass different layers and overlap with each other. Types of the first transistor and the second transistor are the same.

Memory device

Systems and method are provided for a memory circuit that includes a bit cell responsive to a bit line signal line and a bit line bar signal line configured to store a bit of data. A pre-charge circuit is configured to charge one of the bit line and bit line bar signal lines prior to a read operation, where the pre-charge circuit includes a first pre-charge component and a second pre-charge component, the first and second pre-charge components being individually controllable for charging the bit line and bit line bar signal lines.

Multi-stage bit line pre-charge

The present disclosure provides an electronic circuit, a memory device, and a method for operating an electronic circuit. An electronic circuit comprises a driver circuit configured to provide a drive voltage to a word line of the electronic circuit, a suppression circuit electrically connected to the driver circuit and the word line, and a control circuit electrically connected to the suppression circuit. The suppression circuit is configured to generate a voltage drop in the drive voltage. The control circuit controls the suppression circuit.

Electronic circuits, memory devices, and methods for operating an electronic circuit

Disclosed herein are related to memory device including an adaptive word line control circuit. In one aspect, the memory device includes a memory cell and a word line driver coupled to the memory cell through a word line. In one aspect, the memory device includes an adaptive word line control circuit including two or more diodes connected in series, where one of the two or more diodes is coupled to the word line.

Adaptive word line control circuit

A method for 3D voltage type TSV signal transmission, comprising transmitting a full swing signal of data with a first voltage through TSVs for each one of a plurality of slave devices to determine a transmission time required for data transmission to a master device. Then, full swing signal is sensed by the master device for reduce the first voltage to be a small swing signal with lower voltage. Logic '0' signals or logic '1' signals with the lower voltage are transmitted through the TSVs by the plurality of slave devices. It is sharing charge and balancing voltage level to a mean value for the logic &#x201c;1&#x201d; signals or the logic &#x201c;0&#x201d; signals by the master device.

Scheme for 3D voltage type TSV signal transmission

Growing community of inventors

Taipei, Taiwan

Pei-Yuan Li