Taiwan Semiconductor Manufacturing Comp. Ltd.

Pei-Yi Liu

Shy-Jay Lin

Burn Jeng Lin

Wen-Chuan Wang

Jaw-Jung Shin

Cheng-Hung Chen

Jyuh-Fuh Lin

Chih-Han Lin

Shih-Yao Lin

Yuan-Ching Peng

Kuei-Yu Kao

Yu-Bey Wu

Yu-Shan Lu

Chi-Sheng Lai

Wei-Chung Sun

Li-Ting Chen

Yu-Fan Peng

Jing Yi Yan

Cheng-Chi Wu

Wen Chuan Wang

A semiconductor structure includes a semiconductor substrate; fin active regions protruded above the semiconductor substrate; and a gate stack disposed on the fin active regions; wherein the gate stack includes a high-k dielectric material layer, and various metal layers disposed on the high-k dielectric material layer. The gate stack has an uneven profile in a sectional view with a first dimension Dat a top surface, a second dimension Dat a bottom surface, and a third dimension Dat a location between the top surface and the bottom surface, and wherein each of Dand Dis greater than D.

Semiconductor device structure with uneven gate profile

The present disclosure provides one embodiment of an IC method that includes receiving an IC design layout, which has a plurality of main features and a plurality of space blocks. The IC method also includes calculating an optimized block dummy density ratio rto optimize a uniformity of pattern density (UPD), determining a target block dummy density ratio R, determining size, pitch and type of a non-printable dummy feature, generating a pattern for dummy features and adding the dummy features in the IC design layout.

Method of fabricating an integrated circuit with non-printable dummy features

The present disclosure provides one embodiment of an IC method. First pattern densities (PDs) of a plurality of templates of an IC design layout are received. Then a high PD outlier template and a low PD outlier template from the plurality of templates are identified. The high PD outlier template is split into multiple subsets of template and each subset of template carries a portion of PD of the high PD outlier template. A PD uniformity (PDU) optimization is performed to the low PD outlier template and multiple individual exposure processes are applied by using respective subset of templates.

Method of fabricating an integrated circuit with a pattern density-outlier-treatment for optimized pattern density uniformity

Lithography methods disclosed herein accommodate shrinking pattern dimensions. An exemplary method includes receiving a pattern to be transferred to a workpiece by a pattern generator. The pattern generator is divided into a first segment set and a second segment set based on the pattern, such that a collective exposure dose from the first segment set and the second segment set satisfies an exposure dose specified by the pattern. The first segment set is offset from the second segment set in a first direction, and segments in the first segment set and segments in the second segment set are offset from each other in a second direction different than the first direction. The method further includes exposing the workpiece according to the first segment set and the second segment set.

Grid refinement method

A technique for converting design shapes into pixel values is provided. The technique may be used to control a direct-write or other lithographic process performed on a workpiece. In an exemplary embodiment, the method includes receiving, at a computing system, a design database specifying a feature having more than four vertices. The computing system also receives a pixel grid. A set of rectangles corresponding to the feature is determined, and the computing system determines an area of a pixel of the pixel grid overlapped by the feature based on the set of rectangles. In some such embodiments, a lithographic exposure intensity is determined for the pixel based on the area overlapped by the feature, and the lithographic exposure intensity is provided for patterning of a workpiece.

System and technique for rasterizing circuit layout data

The present disclosure provides one embodiment of an IC method that includes receiving an IC design layout, which has a plurality of main features and a plurality of space blocks. The IC method also includes calculating an optimized block dummy density ratio rto optimize an uniformity of pattern density (UPD), determining a target block dummy density ratio R, determining size, pitch and type of a non-printable dummy feature, generating a pattern for non-printable dummy features and adding the non-printable dummy features in the IC design layout.

The present disclosure provides an embodiment of a method, for a lithography process for reducing a critical dimension (CD) by a factor n wherein n&#x3c;1. The method includes providing a pattern generator having a first pixel size S1 to generate an alternating data grid having a second pixel size S2 that is &#x3c;S1, wherein the pattern generator includes multiple grid segments configured to offset from each other in a first direction; and scanning the pattern generator in a second direction perpendicular to the first direction during the lithography process such that each subsequent segment of the grid segments is controlled to have a time delay relative to a preceding segment of the grid segments.

The present disclosure provides one embodiment of an IC method that includes receiving an IC design layout including a plurality of main features; choosing isolation distances to the IC design layout; oversizing the main features according to each of the isolation distances; generating a space block layer for the each of the isolation distances by a Boolean operation according to oversized main features; choosing an optimized space block layer and an optimized block dummy density ratio of the IC design layout according to pattern density variation; generating dummy features in the optimized space block layer according to the optimized block dummy density ratio; and forming a tape-out data of the IC design layout including the main features and the dummy features, for IC fabrication.

Method of fabricating an integrated circuit with block dummy for optimized pattern density uniformity

The present disclosure provides a method that includes receiving an IC design layout having main features and generating a plurality of space block layers to the IC design layout. The method also includes calculating main pattern density PDand dummy pattern density PDof the IC design layout and calculating a least variation block dummy density ratio (LVBDDR) of the IC design layout for each of the space block layers according to the main pattern density and the dummy pattern density. The method further includes choosing an optimized space block layer and an optimized block dummy density ratio according to the LVBDDR and generating a modified IC design layout from the IC design layout according to the optimized space block layer and the optimized block dummy density ratio. Additionally, the method includes forming a tape-out data of the modified IC design layout for IC fabrication.

Method of fabricating an integrated circuit with optimized pattern density uniformity

The present disclosure provides an embodiment of a method, for a lithography process for reducing a critical dimension (CD) by a factor n wherein n&#x3c;1. The method includes providing a pattern generator having a first pixel size Sto generate an alternating data grid having a second pixel size Sthat is &#x3c;S, wherein the pattern generator includes multiple grid segments configured to offset from each other in a first direction; and scanning the pattern generator in a second direction perpendicular to the first direction during the lithography process such that each subsequent segment of the grid segments is controlled to have a time delay relative to a preceding segment of the grid segments.

Growing community of inventors

Changhua, Taiwan

Pei-Yi Liu