Micron Technology Incorporated

Pei Sian Shao

Brandon P Wirz

Bradley R Bitz

Sui Chi Huang

Chun Min Lin

Yu Lin Kao

Semiconductor die assemblies with sidewall protection, and associated methods and systems are disclosed. In one embodiment, a semiconductor die assembly includes an interface die with a low-k dielectric layer and a stack of semiconductor dies attached to the interface die. The semiconductor die assembly also includes a molding structure that protects sidewalls of the interface die and sidewalls of the semiconductor dies. In some embodiments, the semiconductor die assembly includes a passivation layer attached to the interface die opposite to the stack of semiconductor dies. Further, the passivation layer may include a sidewall surface coplanar with an outer sidewall surface of the molding structure. The passivation layer may include a ledge underneath the molding structure, which is uncovered by the interface die. The semiconductor die assembly may include a NCF material at the sidewalls of the stack of semiconductor dies, where the molding structure surrounds the NCF material.

Semiconductor die assemblies with sidewall protection and associated methods and systems

Methods for fabricating microelectronic device assemblies, the method comprising providing mutually spaced stacks of microelectronic devices on a substrate and substantially concurrently encapsulating the stacks of microelectronic devices on the substrate and gang bonding mutually aligned conductive elements of vertically adjacent microelectronic devices. Compression molding apparatus for implementing the methods, and resulting microelectronic device assemblies are also disclosed.

Growing community of inventors

Taichung, Taiwan

Pei Sian Shao