Taiwan Semiconductor Manufacturing Comp. Ltd.

Macronix International Co., Ltd.

Industrial Technology Research Institute

Pei-Ren Jeng

Tze-Liang Lee

Chii-Horng Li

Yee-Chia Yeo

Hsueh-Chang Sung

Chih-Tang Peng

Yen-Ru Lee

Kei-Wei Chen

Tai-Chun Huang

Yan-Ting Lin

Chih-Yun Chin

Ming-Hua Yu

Heng-Wen Ting

Jung-Jen Chen

Bao-Ru Young

Huan-Just Lin

Jin-Aun Ng

Jen-Sheng Yang

Hao-Ming Lien

Yuan-Tien Tu

Ta-Wei Lin

Chih-Yang Yeh

Jung-Hui Kao

Hui-Wen Lin

Ta-Chun Ma

Shih-Hao Lo

Maxi Chang

Harry-Hak-Lay Chuang

Kuang-Yuan Hsu

Chien-Wei Lee

Yen-Chun Huang

Tzu-Hsiang Hsu

Tsai-Jung Ho

Bor Chiuan Hsieh

Ching-Lun Lai

Cheng-Hsiung Yen

Roger Tai

Anthony Lin

Davie Liu

Chien-Chang Su

Yi-Fang Pai

Chih-Pin Tsao

Jung-Chi Tai

Pin-Ju Liang

Ji-Yin Tsai

Hung-Yao Chen

Chia-Ao Chang

Yi-Cheng Li

Shih-Chieh Chang

Li-Ting Wang

De-Wei Yu

Yu-Chang Lin

Chu-Yun Fu

Chyi Shyuan Chern

Cheng-Po Chau

Jeng-Wei Yu

Wen-Pin Lu

Tsai-Fu Hsiao

Meng-Ku Chen

Chun-An Lin

Hung-Yu Chiu

Hsiu-Ting Chen

Yi-Ming Huang

Ping-Yi Chang

U-Way Tseng

Pin-Chu Liang

Yi-Chao Wang

Hsing-Chi Chen

Jui-Hei Huang

Cheng-Chen Huseh

Fu-Hsiang Hsu

Yu-Ling Liou

Chen-Hua Douglas Yu

Syun-Ming Jang Jang

Tien-I Bao

Keng-Chu Lin

Yung-Cheng Lu

Chung-Chi Ko

Yi-Hung Lin

Yuan-Ching Peng

Jiun-Ming Kuo

Shwang-Ming Jeng

Chia-Cheng Chou

Cha-Hsin Lin

Henry Chung

Hak-Lay Chuang

Tsung-Hsi Yang

Che-Yu Lin

Ching-Chiun Wang

Chi-Tung Huang

You-Ting Lin

Ming-Feng Hsieh

Shu-Wen Shen

Chung-Yeh Lee

Hsuan-Ling Kao

Wan-Yi Liu

Chang-Shen Lu

Wen-Miao Lo

Shu-Li Wu

Chung Yeh Lee

A method includes etching a semiconductor substrate to form a trench between a first semiconductor strip and a second semiconductor strip. The first semiconductor strip has a first width at about 5 nm below a top of the first semiconductor strip and a second width at about 60 nm below the top of the first semiconductor strip. The first width is smaller than about 5 nm, and the second width is smaller than about 14.5 nm. The trench is filled with dielectric materials to form an isolation region, which is recessed to have a depth. A top portion of the first semiconductor strip protrudes higher than the isolation region to form a protruding fin. The protruding fin has a height smaller than the depth. A gate stack is formed to extend on a sidewall and a top surface of the protruding fin.

Fin bending reduction through structure design

A method includes forming a fin extending from a substrate; depositing a liner over a top surface and sidewalls of the fin, where the minimum thickness of the liner is dependent on selected according to a first germanium concentration of the fin; forming a shallow trench isolation (STI) region adjacent the fin; removing a first portion of the liner on sidewalls of the fin, the first portion of the liner being above a topmost surface of the STI region; and forming a gate stack on sidewalls and a top surface of the fin, where the gate stack is in physical contact with the liner.

Semiconductor method and device

In an embodiment, a method includes forming a first fin and a second fin within an insulation material over a substrate, the first fin and the second fin includes different materials, the insulation material being interposed between the first fin and the second fin, the first fin having a first width and the second fin having a second width; forming a first capping layer over the first fin; and forming a second capping layer over the second fin, the first capping layer having a first thickness, the second capping layer having a second thickness different from the first thickness.

Semiconductor device and methods of manufacturing

In an embodiment, a device includes: a substrate; a first semiconductor region extending from the substrate, the first semiconductor region including silicon; a second semiconductor region on the first semiconductor region, the second semiconductor region including silicon germanium, edge portions of the second semiconductor region having a first germanium concentration, a center portion of the second semiconductor region having a second germanium concentration less than the first germanium concentration; a gate stack on the second semiconductor region; and source and drain regions in the second semiconductor region, the source and drain regions being adjacent the gate stack.

Semiconductor device and method

A method of forming a fin field-effect transistor device includes: forming a gate structure over a first fin and a second fin; forming, on a first side of the gate structure, a first recess and a second recess in the first fin and the second fin, respectively; and forming a source/drain region in the first and second recesses, which includes: forming a barrier layer in the first and second recesses; forming a first epitaxial material over the barrier layer, where a first portion of the first epitaxial material over the first fin is spaced apart from a second portion of the first epitaxial material over the second fin; forming a second epitaxial material over the first and second portions of the first epitaxial material, where the second epitaxial material extends continuously from the first fin to the second fin; and forming a capping layer over the second epitaxial material.

Fin field-effect transistor device and method of forming

A system and methods of manufacturing semiconductor devices is described herein. The method includes forming a recess between fins in a substrate and forming a dielectric layer over the fins and in the recess. Once the dielectric layer has been formed, a bottom seed structure is formed over the dielectric layer within the recess and the dielectric layer is exposed along sidewalls of the recess. A dummy gate material is grown from the bottom seed structure in a bottom-up deposition process without growing the dummy gate material from the dielectric layer exposed along sidewalls of the recess.

System and methods of manufacturing semiconductor devices

A method includes forming a semiconductor fin protruding higher than a top surface of an isolation region. The semiconductor fin overlaps a semiconductor strip, and the semiconductor strip contacts the isolation region. The method further includes forming a gate stack on a sidewall and a top surface of a first portion of the semiconductor fin, and etching the semiconductor fin and the semiconductor strip to form a trench. The trench has an upper portion in the semiconductor fin and a lower portion in the semiconductor strip. A semiconductor region is grown in the lower portion of the trench. Process gases used for growing the semiconductor region are free from both of n-type dopant-containing gases and p-type dopant-containing gases. A source/drain region is grown in the upper portion of the trench, wherein the source/drain region includes a p-type or an n-type dopant.

Method for forming an undoped region under a source/drain

An apparatus includes a vacuum chamber, a wafer transfer mechanism, a first gas source, a second gas source and a reuse gas pipe. The vacuum chamber is divided into at least three reaction regions including a first reaction region, a second reaction region and a third reaction region. The wafer transfer mechanism is structured to transfer a wafer from the first reaction region to the third reaction region via the second reaction region. The first gas source supplies a first gas to the first reaction region via a first gas pipe, and a second gas source supplies a second gas to the second reaction region via a second gas pipe. The reuse gas pipe is connected between the first reaction region and the third reaction region for supplying an unused first gas collected in the first reaction region to the third reaction region.

Apparatus for manufacturing a thin film and a method therefor

A semiconductor device having an improved source/drain region profile and a method for forming the same are disclosed. In an embodiment, a method includes etching one or more semiconductor fins to form one or more recesses; and forming a source/drain region in the one ore more recesses, the forming the source/drain region including epitaxially growing a first semiconductor material in the one or more recesses at a temperature of 600° C. to 800° C., the first semiconductor material including doped silicon germanium; and conformally depositing a second semiconductor material over the first semiconductor material at a temperature of 300° C. to 600° C., the second semiconductor material including doped silicon germanium and having a different composition than the first semiconductor material.

Semiconductor device and method of manufacture

Protective layer over FinFET and method of forming same

A device is manufactured by providing a semiconductor fin protruding from a major surface of a silicon substrate comprising silicon. A liner and a shallow trench isolation (STI) region are formed adjacent the semiconductor fin. A silicon cap is deposited over the semiconductor fin. The resulting cap consists of crystalline silicon in the portion over the semiconductor fin and consists of amorphous silicon in the portions over the liner and STI region. An HCl etch bake process is performed to remove the portions of amorphous silicon over the liner and the STI region.

An embodiment is a semiconductor structure. The semiconductor structure includes a fin on a substrate. A gate structure is over the fin. A source/drain is in the fin proximate the gate structure. The source/drain includes a bottom layer, a supportive layer over the bottom layer, and a top layer over the supportive layer. The supportive layer has a different property than the bottom layer and the top layer, such as a different material, a different natural lattice constant, a different dopant concentration, and/or a different alloy percent content.

Supportive layer in source/drains of FinFET devices

A method includes depositing a first dielectric layer in an opening, the first dielectric layer comprising a semiconductor element and a non-semiconductor element. The method further includes depositing a semiconductor layer on the first dielectric layer, the semiconductor layer comprising a first element that is the same as the semiconductor element. The method further includes introducing a second element to the semiconductor layer wherein the second element is the same as the non-semiconductor element. The method further includes applying a thermal annealing process to the semiconductor layer to change the semiconductor layer into a second dielectric layer.

Seamless gap fill

An embodiment is a semiconductor structure. The semiconductor structure includes a substrate. A fin is on the substrate. The fin includes silicon germanium. An interfacial layer is over the fin. The interfacial layer has a thickness in a range from greater than 0 nm to about 4 nm. A source/drain region is over the interfacial layer. The source/drain region includes silicon germanium.

Interfacial layer between fin and source/drain region

A method includes depositing a first dielectric layer over and along sidewalls of a first semiconductor fin and a second semiconductor fin, depositing a second dielectric layer over the first dielectric layer, recessing the first dielectric layer to define a dummy fin between the first semiconductor fin and the second semiconductor fin, forming a cap layer over top surfaces and sidewalls of the first semiconductor fin and the second semiconductor fin, wherein the forming the cap layer comprises depositing the cap layer in a furnace at process temperatures higher than a first temperature, and lowering the temperature of the furnace, wherein during the lowering the temperature of the furnace, the pressure in the furnace is raised to and maintained at 10 torr or higher until the temperature of the furnace drops below the first temperature.

Growth process and methods thereof

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Chu-Bei, Taiwan

Pei-Ren Jeng