Industrial Technology Research Institute

Pei-Jer Tzeng

Lurng-Shehng Lee

Cha-Hsin Lin

Jui-Chin Chen

Tzu-Kun Ku

Hengyuan Lee

Ching Chiun Wang

Jenn-Gwo Hwu

Heng-Yuan Lee

Po-Chun Yeh

Kuan-Wei Chen

Wen Chun Wang

Chien-Chou Chen

Chieh-Shuo Liang

Yu-De Lin

Yu-Chen Hsin

Po-Chih Chang

Chung-Chih Wang

Yiu-Hsiang Chang

Maikap Siddheswar

Chih-Sheng Kuo

A ferroelectric memory includes a first electrode, a second electrode opposite to the first electrode, a ferroelectric composite layer disposed between the first electrode and the second electrode, and a first insulating layer disposed on one side of the ferroelectric composite layer. The ferroelectric composite layer includes a first electrode layer, a second electrode layer, a ferroelectric layer and an antiferroelectric layer. The first electrode layer is opposite to the second electrode layer, and the ferroelectric layer and the antiferroelectric layer are disposed between the first electrode layer and the second electrode layer.

Ferroeolectric memories with ferroelectric composite layer

A structure of an electrochemical unit includes a substrate, a first metal layer disposed on the substrate, and an array of electrochemical cells disposed on the first metal layer. The array of the electrochemical cells includes a plurality of electrochemical cells. Each of the electrochemical cells includes the first metal layer disposed on the substrate, a first electrode disposed on the first metal layer, a polymer layer disposed on the substrate and adjacent to the first metal layer and the first electrode. A second metal layer is disposed on the polymer layer, and a second electrode is disposed on the second metal layer. A pore is constituted between the polymer layers of every the two electrochemical cells. A cavity located above the first electrode is defined between every the two electrochemical cells, wherein the cavity is communicated with the pore.

Structures and manufacture method of electrochemical units

A liquid-sensing apparatus includes a substrate, partitions, and independent sensors. The partitions are disposed on the substrate for separating several housing spaces in order to respectively house a to-be-detected liquid, wherein each of the housing spaces has a bottom, a closed sidewall, and an open top, and thus the to-be-detected liquid may be dripped from the top of the housing space. The independent sensors are respectively formed at the bottom of different housing spaces, wherein the independent sensors respectively include different sensing material layers, and surfaces of the different sensing material layers have nanoholes.

Liquid-sensing apparatus and method of manufacturing the same

A bonding structure including a first substrate, a second substrate, and an adhesive layer is provided. The first substrate has a plurality of first trenches. The adhesive layer is located between the first substrate and the second substrate, and the first trenches are filled with the adhesive layer.

Wafer bonding method and device with reduced thermal expansion

The disclosure provides a TSV substrate structure and the stacked assembly of a plurality of the substrate structures, the TSV substrate structure including: a substrate comprising a first surface, a corresponding second surface, and a TSV communicating the first surface with the second surface through the substrate; and a conductor unit completely filling the TSV, the conductor unit comprising a conductor body which has a first and a second ends corresponding to the first and second surfaces of the substrate, respectively.

TSV substrate structure and the stacked assembly thereof

A method for forming a capacitor comprises providing a substrate. A bottom electrode material layer is formed on the substrate. A first mask layer is formed on the bottom electrode material layer. A second mask layer is formed on the first mask layer. The second mask layer is patterned to form a patterned second mask layer in a predetermined region for formation of a capacitor. A plurality of hemispherical grain structures are formed on a sidewall of the patterned second mask layer. The first mask layer is etched by using the hemispherical grain structures and the patterned second mask layer as a mask, thereby forming a patterned first mask layer having a pattern. The pattern of the first mask layer is transferred to the bottom electrode material layer. And, a capacitor dielectric layer and a top electrode layer are formed on the bottom electrode material layer to form the capacitor.

Methods for fabricating a capacitor

A non-volatile memory device and fabricating method thereof are provided. In the deposition to form a tunneling dielectric layer, a composite charge trapping layer and a block dielectric layer, an ingredient of a depositing material or the depositing material is adjusted to form a grading energy level structure, such that carriers are trapped or erased more easily in accordance with a variation in grading energy level. Therefore, the carriers are stored more effectively and the probability that the electric leakage occurs is reduced substantially.

Non-volatile memory device and fabricating method thereof

A method of fabricating a dielectric piece which includes metal compound dots is provided. A stacked layer formed over the substrate includes a metal compound layer and an energy barrier layer. A process such as an oxidization annealing process is then performed so that the metal compound layer is transformed into a great number of crystalline metal compound dots distributed in the energy barrier layer.

Method of fabricating metal compound dots dielectric piece

A method of manufacturing a charge storage device is provided. Utilizing the capacity for a precise control of the thickness and the silicon content of a deposited film in an atomic layer deposition process, a stacked gradual material layer such as a hafnium silicon oxide (HfSiO) layer is formed. The silicon content is gradually changed throughout the duration of the HfSiOdeposition process. The etching rate for the HfSiOlayer in dilute hydrogen fluoride solution is dependent on the silicon content y in the HfSiOlayer. The sidewalls of the stacked gradual material layer are etched to form an uneven profile. The lower electrode, the capacitor dielectric layer and the upper electrode are formed on the uneven sidewalls of the stacked gradual material layers, the area between the lower electrode and the upper electrode is increased to improve the capacitance of the charge storage device.

Method of manufacturing charge storage device

A process of forming a high-k gate dielectric layer is applied in forming semiconductor devices such as metal oxide semiconductor transistor or memory devices. A metal layer such as Hf or Zr is formed on a substrate. The substrate is then dipped in an acidic solution such as a nitric acid aqueous solution to form a high-K metal oxide layer including oxides or silicate with a predetermined thickness. Thereby, leakage current is effectively reduced to meet the requirement of currently technology nodes.

Growing community of inventors

Hsinchu, Taiwan

Pei-Jer Tzeng