Taiwan Semiconductor Manufacturing Comp. Ltd.

Parabellum Strategic Opportunities Fund LLC

Pei-Hsun Wang

Chih-Hao Wang

Chun-Hsiung Lin

Kuo-Cheng Chiang

Chih-Chao Chou

Jui-Chien Huang

Jung-Hung Chang

Shih-Cheng Chen

Lo-Heng Chang

Kuo-Cheng Ching

Ching-Wei Tsai

Chia-Hao Chang

Zhi-Chang Lin

Pei-Yu Wang

Wei-Sheng Yun

Chen-Han Wang

Kuan-Lun Cheng

Yu-Xuan Huang

Cheng-Ting Chung

Min Cao

The present disclosure provides a semiconductor device that includes a semiconductor fin disposed over a substrate, an isolation structure at least partially surrounding the fin, an epitaxial source/drain (S/D) feature disposed over the semiconductor fin, where an extended portion of the epitaxial S/D feature extends over the isolation structure, and a silicide layer disposed on the epitaxial S/D feature, where the silicide layer covers top, bottom, sidewall, front, and back surfaces of the extended portion of the S/D feature.

FET with wrap-around silicide and fabrication methods thereof

A semiconductor device according to the present disclosure includes a first isolation feature and a second isolation feature, a fin structure extending lengthwise along a first direction and sandwiched between the first isolation feature and the second isolation feature along a second direction perpendicular to the first direction, a first channel member disposed over the first isolation feature, a second channel member disposed over the second isolation feature, and a gate structure disposed over and wrapping around the first channel member and the second channel member.

Transistors having vertical nanostructures

The present disclosure provides a semiconductor device. The semiconductor device includes a semiconductor fin over a substrate, an epitaxial source/drain (S/D) feature disposed over the semiconductor fin, first and second dielectric layers over the substrate, and an S/D contact disposed on the epitaxial S/D feature. The first and second dielectric layers have different material compositions. A first sidewall of the epitaxial S/D feature is facing the first dielectric layer, a second sidewall of the epitaxial S/D feature is facing the second dielectric layer, and the S/D contact partially covers a top surface of the epitaxial S/D feature and extends continuously to cover the first sidewall of the epitaxial S/D feature.

Self-aligned source/drain metal contact

A method for forming a semiconductor device structure is provided. The method includes forming a gate stack over a substrate. The substrate has a base and a multilayer structure over the base, and the gate stack wraps around the multilayer structure. The method includes partially removing the multilayer structure, which is not covered by the gate stack. The multilayer structure remaining under the gate stack forms a multilayer stack, and the multilayer stack includes a sacrificial layer and a channel layer over the sacrificial layer. The method includes partially removing the sacrificial layer to form a recess in the multilayer stack. The method includes forming an inner spacer layer in the recess and a bottom spacer over a sidewall of the channel layer. The method includes forming a source/drain structure over the bottom spacer. The bottom spacer separates the source/drain structure from the channel layer.

Semiconductor device structure and method for forming the same

A semiconductor device is provided. The semiconductor device includes a plurality of channel layers stacked over a semiconductor substrate and spaced apart from one another, a source/drain structure adjoining the plurality of channel layers, a gate structure wrapping around the plurality of channel layers, and a first inner spacer between the gate structure and the source/drain structure and between the plurality of channel layers. The first inner spacer is made of an oxide of a semiconductor material.

Methods of fabricating semiconductor devices having gate-all-around structure with inner spacer last process

A device includes a first semiconductor strip protruding from a substrate, a second semiconductor strip protruding from the substrate, an isolation material surrounding the first semiconductor strip and the second semiconductor strip, a nanosheet structure over the first semiconductor strip, wherein the nanosheet structure is separated from the first semiconductor strip by a first gate structure including a gate electrode material, wherein the first gate structure partially surrounds the nanosheet structure, and a first semiconductor channel region and a semiconductor second channel region over the second semiconductor strip, wherein the first semiconductor channel region is separated from the second semiconductor channel region by a second gate structure including the gate electrode material, wherein the second gate structure extends on a top surface of the second semiconductor strip.

Hybrid channel semiconductor device and method

A semiconductor structure includes a fin disposed on a substrate, the fin including a channel region comprising a plurality of channels vertically stacked over one another, the channels comprising germanium distributed therein. The semiconductor structure further includes a gate stack engaging the channel region of the fin and gate spacers disposed between the gate stack and the source and drain regions of the fin, wherein each channel of the channels includes a middle section wrapped around by the gate stack and two end sections engaged by the gate spacers, wherein a concentration of germanium in the middle section of the channel is higher than a concentration of germanium in the two end sections of the channel, and wherein the middle section of the channel further includes a core portion and an outer portion surrounding the core portion with a germanium concentration profile from the core portion to the outer portion.

Dual channel gate all around transistor device and fabrication methods thereof

Provided are FinFET devices and methods of forming the same. A FinFET device includes a substrate, a first gate strip and a second gate strip. The substrate has at least one first fin in a first region, at least one second fin in a second region and an isolation layer covering lower portions of the first and second fins. The first fin includes a first material layer and a second material layer over the first material layer, and the interface between the first material layer and the second material layer is uneven. The first gate strip is disposed across the first fin. The second gate strip is disposed across the second fin.

FinFET devices and methods of forming the same

Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary method comprises forming a fin over a substrate, wherein the fin comprises a first semiconductor layer and a second semiconductor layer including different semiconductor materials, and the fin comprises a channel region and a source/drain region; forming a dummy gate structure over the channel region of the fin and over the substrate; etching a portion of the fin in the source/drain region to form a trench therein, wherein a bottom surface of the trench is below a bottom surface of the second semiconductor layer; selectively removing an edge portion of the second semiconductor layer in the channel region such that the second semiconductor layer is recessed; forming a sacrificial structure around the recessed second semiconductor layer and over the bottom surface of the trench; and epitaxially growing a source/drain feature in the source/drain region of the fin.

Gate-all-around structure and methods of forming the same

Methods for manufacturing a semiconductor structure are provided. The method includes alternately stacking first semiconductor material layers and second semiconductor layers over a substrate and patterning the first semiconductor material layers and the second semiconductor layers to form a first fin structure and a second fin structure. The method also includes forming an insulating layer around the first fin structure and the second fin structure and forming a dielectric fin structure over the insulating layer and spaced apart from the first fin structure and the second fin structure. The method also includes forming a first source/drain structure attached to the first fin structure and forming a semiconductor layer covering the first source/drain structure. The method also includes oxidizing the semiconductor layer to form an oxide layer and forming a second source/drain structure attached to the second fin structure after the oxide layer is formed.

Gate all around structure with additional silicon layer and method for forming the same

A method includes forming an epitaxy semiconductor layer over a semiconductor substrate, and etching the epitaxy semiconductor layer and the semiconductor substrate to form a semiconductor strip, which includes an upper portion acting as a mandrel, and a lower portion under the mandrel. The upper portion is a remaining portion of the epitaxy semiconductor layer, and the lower portion is a remaining portion of the semiconductor substrate. The method further includes growing a first semiconductor fin starting from a first sidewall of the mandrel, growing a second semiconductor fin starting from a second sidewall of the mandrel. The first sidewall and the second sidewall are opposite sidewalls of the mandrel. A first transistor is formed based on the first semiconductor fin. A second transistor is formed based on the second semiconductor fin.

Hybrid source drain regions formed based on same fin and methods forming same

A semiconductor device includes a substrate, a plurality of nanosheets, a plurality of source/drain (S/D) features, and a gate stack. The substrate includes a first fin and a second fin. The first fin has a first width less than a second width of the second fin. The plurality of nanosheets is disposed on the first fin and the second fin. The plurality of source/drain (S/D) features are located on the first fin and the second fin and abutting the plurality of nanosheets. A bottom surface of the plurality of source/drain (S/D) features on the first fin is equal to or lower than a bottom surface of the plurality of source/drain (S/D) features on the second fin. The gate stack wraps each of the plurality of nanosheets.

Multi-gate devices and method of fabricating the same

A semiconductor device and a method of forming the same are provided. A semiconductor device according to the present disclosure includes a first source/drain feature, a second source/drain feature, a first semiconductor channel member and a second semiconductor channel member extending between the first and second source/drain features, and a first dielectric feature and a second dielectric feature each including a first dielectric layer and a second dielectric layer different from the first dielectric layer. The first and second dielectric features are sandwiched between the first and second semiconductor channel members.

Inner spacers for gate-all-around transistors

A semiconductor device is provided. The semiconductor device includes a fin protruding from a semiconductor substrate and a gate structure formed across the fin. The semiconductor device also includes a gate spacer formed over a sidewall of the gate structure. The gate spacer includes a sidewall spacer and a sealing spacer formed above the sidewall spacer. In addition, an air gap is vertically sandwiched between the sidewall spacer and the sealing spacer. The semiconductor device further includes a hard mask formed over the gate structure and covering a sidewall of the sealing spacer.

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Kaohsiung, Taiwan

Pei-Hsun Wang