Taiwan Semiconductor Manufacturing Comp. Ltd.

Pei-Hsuan Lee

Chih-Chien Chi

Chien-Ling Hwang

Ching-Hua Hsieh

Chen-Hua Douglas Yu

Hung-Wen Su

Hao-Yi Tsai

Tin-Hao Kuo

Chien Ling Hwang

Yu-Chia Lai

Shu-Rong Chun

Yu-Ting Chiu

Jui-Chang Kuo

Chung-Shi Liu

Kuo Lung Pan

Hsiao-Kuan Wei

Hsin-Yun Hsu

Jui-Fen Chien

Kuang-Shing Chen

Yu-Hsuan Huang

Chuei-Tang Wang

Chao-Wen Shih

Han-Ping Pu

Chung-Hao Tsai

Po-Yuan Teng

Tzu-Chun Tang

Kuo-Lung Pan

Albert Wan

Chien-Hsiang Huang

Kuan-Hsin Chen

Chun-Chieh Chin

Po-Hsiang Huang

Hui Yu Lee

Chih-Hsuan Tai

Wen-Sheh Huang

Su-Jen Sung

Chia-Hung Liu

Chih-Hsiang Chang

Szu-Hua Wu

Jung-Tang Wu

Jen Hung Wang

Yen-Chun Lin

Chi-Feng Lin

Hsiao-Chung Liang

Shu-Cheng Chin

Shang-Wei Fang

Yuan-Yao Chang

Sung-Yueh Wu

Ting-Hua Hsieh

Jen-Chun Liao

Ming-Yuan Gao

Hsin-Ying Peng

Jing-Sen Wang

Chen-Yi Niu

Wei-Ray Lin

Pao-Sheng Chen

Yeong-Jyh Lin

Chien-Liang Chen

Ying-Jui Huang

Yu-Hsiang Cheng

Chia-Chia Kan

Hung-Ming Chen

Xiaomeng Chen

Yu-Ying Liu

A manufacturing method of a package system includes: providing a base plate with a first thermal interface material (TIM) layer; placing a semiconductor package on the first TIM layer over the base plate, wherein the semiconductor package comprises a plurality of packaging units arranged in an array and a plurality of electrical connectors surrounding the array of the plurality of packaging units; stacking a gasket and a top plate on the array of the plurality of packaging units, wherein the gasket is interposed between the top plate and the array of the plurality of packaging units; and securing the top plate, the gasket, the plurality of packaging units, and the base plate together through a plurality of fasteners, wherein each of the plurality of fasteners is arranged at a gap between two of the adjacent packaging units.

Package system and manufacturing method thereof

In an embodiment, a device includes: a package component including integrated circuit dies, an encapsulant around the integrated circuit dies, a redistribution structure over the encapsulant and the integrated circuit dies, and sockets over the redistribution structure; a mechanical brace physically coupled to the sockets, the mechanical brace having openings, each one of the openings exposing a respective one of the sockets; a thermal module physically and thermally coupled to the encapsulant and the integrated circuit dies; and bolts extending through the thermal module, the mechanical brace, and the package component.

Integrated circuit package and method

The present disclosure provides a method and a system for scanning wafer. The system captures a defect image of a wafer, and generates a reference image corresponding to the first defect image based on a reference image generation model. The system generates a defect marked image based on the defect image and the reference image.

Method and system for scanning wafer

A package structure includes a carrier substrate, a die, and an encapsulant. The carrier substrate includes through carrier vias (TCV). The die is disposed over the carrier substrate. The die includes a semiconductor substrate and conductive posts disposed over the semiconductor substrate. The conductive posts face away from the carrier substrate. The encapsulant laterally encapsulates the die.

Package structure and manufacturing method thereof

A method of manufacturing an interconnect structure includes forming an opening through a dielectric layer. The opening exposes a top surface of a first conductive feature. The method further includes forming a barrier layer on sidewalls of the opening, passivating the exposed top surface of the first conductive feature with a treatment process, forming a liner layer over the barrier layer, and filling the opening with a conductive material. The liner layer may include ruthenium.

Method of forming interconnect structure having a barrier layer

Interconnect structures exhibiting reduced accumulation of copper vacancies along interfaces between contact etch stop layers (CESLs) and interconnects, along with methods for fabrication, are disclosed herein. A method includes forming a copper interconnect in a dielectric layer and depositing a metal nitride CESL over the copper interconnect and the dielectric layer. An interface between the metal nitride CESL and the copper interconnect has a first surface nitrogen concentration, a first nitrogen concentration and/or a first number of nitrogen-nitrogen bonds. A nitrogen plasma treatment is performed to modify the interface between the metal nitride CESL and the copper interconnect. The nitrogen plasma treatment increases the first surface nitrogen concentration to a second surface nitrogen concentration, the first nitrogen concentration to a second nitrogen concentration, and/or the first number of nitrogen-nitrogen bonds to a second number of nitrogen-nitrogen bonds, each of which minimizes accumulation of copper vacancies at the interface.

Nitrogen plasma treatment for improving interface between etch stop layer and copper interconnect

A method of manufacturing an electronic device includes providing a core dielectric layer with two conductive layers formed on two opposite surfaces of the core dielectric layer, and removing at least a portion of each of the two conductive layers to respectively form an antenna pattern and a circuit pattern of a chip package at the two opposite surfaces of the core dielectric layer.

Electronic device and manufacturing method thereof

In a semiconductor manufacturing method includes providing a plurality of patterns on a semiconductor substrate. The patterns include an NMOS structure arranged next to an N/N well structure, and/or a PMOS structure arranged next to a P/P well structure. The method further includes: receiving a plurality of images by applying an electron beam to the patterns; and transferring the semiconductor substrate to a next process step if there is no image conversion according to a predetermined image contrast property of the patterns.

In-line electrical detection of defects at wafer level

A package system and a manufacturing method thereof are provided. The package system includes a semiconductor package and a thermal-dissipating structure. The semiconductor package includes a first surface and a second surface opposing to each other, and a planarity of the second surface is greater than that of the first surface. The thermal-dissipating structure includes a first plate secured to the semiconductor package, a gasket interposed between the first plate and the semiconductor package, a second plate secured to the semiconductor package opposite to the first plate, and a first thermal interface material layer interposed between the second plate and the second surface of the semiconductor package. The gasket includes a plurality of hollow regions corresponding to portions of the first surface of the semiconductor package.

In an embodiment, a device includes: a package component including: integrated circuit dies; an encapsulant around the integrated circuit dies; a redistribution structure over the encapsulant and the integrated circuit dies, the redistribution structure being electrically coupled to the integrated circuit dies; sockets over the redistribution structure, the sockets being electrically coupled to the redistribution structure; and a support ring over the redistribution structure and surrounding the sockets, the support ring being disposed along outermost edges of the redistribution structure, the support ring at least partially laterally overlapping the redistribution structure.

Integrated circuit packages having support rings

A high atomic number material is applied to one or more surfaces of a semiconductor structure of a wafer. The one or more surfaces are at a depth different from a depth of a surface of the wafer. An electron beam is scanned over the semiconductor structure to cause a backscattered electron signal to be collected at a collector. A profile scan of the semiconductor structure is generated based on an intensity of the backscattered electron signal, at the collector, resulting from the high atomic number material. The high atomic number material increases the intensity of the backscattered electron signal for the one or more surfaces of the semiconductor structure such that contrast in the profile scan is increased. The increased contrast of the profile scan enables accurate critical dimension measurements of the semiconductor structure.

Semiconductor structure inspection using a high atomic number material

Embodiments disclosed herein relate generally to capping processes and structures formed thereby. In an embodiment, a conductive feature, formed in a dielectric layer, has a metallic surface, and the dielectric layer has a dielectric surface. The dielectric surface is modified to be hydrophobic by performing a surface modification treatment. After modifying the dielectric surface, a capping layer is formed on the metallic surface by performing a selective deposition process. In another embodiment, a surface of a gate structure is exposed through a dielectric layer. A capping layer is formed on the surface of the gate structure by performing a selective deposition process.

Selective capping processes and structures formed thereby

A method for forming a semiconductor device, includes: forming a metal layer on a semiconductor substrate; forming a dielectric layer over the metal layer; etching a top portion of the dielectric layer; after etching the top portion of the dielectric layer, removing first mist from a bottom portion of the dielectric layer; removing the bottom portion of the dielectric layer to expose the metal layer; performing a pre-clean operation, using an alcohol base vapor or an aldehyde base vapor, on the dielectric layer and the metal layer; and forming a conductor extending through the dielectric layer and in contact with the metal layer.

Method for forming semiconductor device

A package structure includes a carrier substrate, a die, and a first redistribution structure. The carrier substrate has a first surface and a second surface opposite to the first surface. The carrier substrate includes an insulating body and through carrier vias (TCV) embedded in the insulating body. The die is disposed over the firs surface of the carrier substrate. The die is electrically connected to the TCVs. The first redistribution structure is disposed on the second surface of the carrier substrate.

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Taipei, Taiwan

Pei-Hsuan Lee