Taiwan Semiconductor Manufacturing Comp. Ltd.

Vanguard International Semiconductor Corporation

Pei-Haw Tsao

Li-Huan Chu

Chender Huang

Tsung-Hsing Lu

Ken Hui Chen

Tsui-Mei Chen

Kuo-Chin Chang

Hank Huang

Jones Wang

Liang-Chen Lin

Tsung-Jen Liao

Pao-Kang Niu

Chung-Yu Wang

Bill Kiang

Chung Yu Wang

Shyue-Ter Leu

Hao-Yi Tsai

Chen-Shien Chen

Chien-Jung Wang

Chao-Yuan Su

Fu-Jen Li

Heh-Chang Huang

An-Tai Xu

Huang-Ting Hsiao

I-Tai Liu

Shin-Puu Jeng

Han-Ping Pu

Cheng-Hung Tsai

Jun He

Chuen-Jye Lin

Shang-Yun Hou

Chenming Hu

Hsin-Yu Pan

Hsin-Hui Lee

Chung-Yi Lin

Chien-Cheng Chen

Nai-Cheng Lu

Shang Y Hou

Shih-Hsing Lin

Daniel Chang

Chengder Huang

Yu-Jung Lin

Sung-Sheng Chiu

Allan Lin

Jeffrey Hsu

Chen-Hua Douglas Yu

Hsien-Wei Chen

Szu-Wei Lu

Mirng-Ji Lii

Ying-Ju Chen

Chien-Hsun Lee

Chien-Li Kuo

Kuo-Chio Liu

Chien-Hsiun Lee

Yu-Wen Liu

Chih-Chiang Chen

Clinton Chao

Cheng-Chung Chang

Han-Liang Tseng

Yu-Chen Hsu

Jing Ruei Lu

Chien-Chun Wang

Rung-De Wang

Yung-Kuan Hsiao

Cheng-Te Lin

Jan-Her Horng

Ju-Min Chen

Shang-Yu Hou

Chia-Hsiung Hsu

Chen-Der Huang

Ken Chen

Chen-Ming Kuo

Kai-Heng Chen

Sean Lin

Chia-Shun Js Hsiao

Lin Yu-Ting

A method of forming an integrated circuit package includes: attaching a first carrier to a package component, the package component including: an interposer; a first semiconductor die attached to a first side of the interposer; a second semiconductor die attached to the first side of the interposer; an encapsulant encapsulating the first semiconductor die and the second semiconductor die; and conductive connectors attached to a second side of the interposer; attaching a second carrier to a package substrate, the package substrate including bond pads; bonding the conductive connectors of the package component to the bond pads of the package substrate by reflowing the conductive connectors while the first carrier is attached to the package component and while the second carrier is attached to the package substrate; removing the first carrier; and removing the second carrier.

Method of forming integrated circuit packages by bonding package component having first carrier to package substrate having second carrier

A chip structure is provided. The chip structure includes a substrate. The chip structure includes an interconnect layer over the substrate. The chip structure includes a conductive pad over the interconnect layer. The chip structure includes a conductive bump over the conductive pad. The conductive bump has a first portion, a second portion, and a neck portion between the first portion and the second portion, the first portion is between the neck portion and the conductive pad, and the neck portion is narrower than both of the first portion and the second portion. The chip structure includes a support layer over the second portion of the conductive bump. A first composition of the support layer is different from a second composition of the conductive bump. The chip structure includes a solder structure over the support layer.

Chip structure

A semiconductor device package and a method of forming the same are provided. The semiconductor device package includes a package substrate having a first surface and a second surface opposite to the first surface. Several integrated devices are bonded to the first surface of the package substrate. A first underfill element is disposed over the first surface and surrounds the integrated devices. A first molding layer is disposed over the first surface and surrounds the integrated devices and the first underfill element. A semiconductor die is bonded to the second surface of the package substrate. A second underfill element is disposed over the second surface and surrounds the semiconductor die. A second molding layer is disposed over the second surface and surrounds the semiconductor die and the second underfill element. Several conductive bumps are disposed over the second surface and adjacent to the second molding layer.

Semiconductor device package having warpage control

A chip package structure is provided. The chip package structure includes a first chip structure including a substrate and an interconnect layer over the substrate. The chip package structure includes a second chip structure over the interconnect layer. The chip package structure includes a first conductive bump connected between the interconnect layer and the second chip structure. The chip package structure includes a conductive pillar over the interconnect layer, wherein a first thickness of the conductive pillar is substantially equal to a sum of a second thickness of the second chip structure and a third thickness of the first conductive bump. The chip package structure includes a molding layer over the interconnect layer and surrounding the second chip structure, the first conductive bump, and the conductive pillar. The chip package structure includes a second conductive bump over a first surface of the conductive pillar.

Method for forming chip package structure

A semiconductor structure includes a first device and a second device bonded on the first device. The first device has a first sidewall distal to the second device and a second sidewall proximal to the second device. A surface roughness of the second sidewall is larger than a surface roughness of the first sidewall. The second device has a third sidewall proximal to the first device and a fourth sidewall distal to the first device. A surface roughness of the fourth sidewall is larger than a surface roughness of the third sidewall.

Dicing method for stacked semiconductor devices

A package structure is provided, including a substrate, a first passivation layer, a metallization layer, a second passivation layer, and a polymer layer. The first passivation layer is formed over the substrate. The metallization layer is conformally formed on the first passivation layer. The second passivation layer is conformally formed on the first passivation layer and the metallization layer. A step structure is formed on the top surface of the second passivation layer, and includes at least one lower part that is lower than the other parts of the step structure. The polymer layer is formed over the second passivation layer. A portion of the polymer layer extends into the lower part of the step structure to engage with the step structure.

Wafer level package with polymer layer delamination prevention design and method of forming the same

Generally, the present disclosure provides example embodiments relating to a package that may be attached to a printed circuit board (PCB). In an embodiment, a structure includes a package. The package includes one or more dies and metal pads on an exterior surface of the package. At least some of the metal pads are first solder ball pads. The structure further includes pins, and each of the pins is attached to a respective one of the metal pads.

Package and printed circuit board attachment

An integrated fan-out structure on a semiconductor die, method of making the same and method of testing the semiconductor die are disclosed. The semiconductor die includes a bond pad and a hole formed in the bond pad, a passivation layer formed over a portion of the bond pad, and a protective layer formed over the hole in the bond pad.

Integrated fan-out structures and methods for forming the same

A semiconductor structure includes a first device and a second device bonded on the first device. The first device has a first sidewall distal to the second device and a second sidewall proximal to the second device. A surface roughness of the second sidewall is larger than a surface roughness of the first sidewall.

Stacked semiconductor devices and methods of forming thereof

The current disclosure describes carrier tape systems, which include a cover tape having adhesion areas and non-adhesion areas which are substantially free of adhesive. Methods for supplying semiconductor devices to an apparatus, which in operation, places the semiconductor devices at desired locations are also described. Methods of forming a semiconductor device carrier system are also described.

Carrier tape system and components and methods of use

A non-conductive magnetic shield material is provided for use in magnetic shields of semiconductor packaging. The material is made magnetic by the incorporation of ferromagnetic particles into a polymer matrix, and is made non-conductive by the provision of an insulating coating on the ferromagnetic particles.

Magnetic shielding material with insulator-coated ferromagnetic particles

Semiconductor device package having warpage control and method of forming the same

A chip structure is provided. The chip structure includes a substrate. The chip structure includes an interconnect layer over the substrate. The chip structure includes a conductive pad over the interconnect layer. The chip structure includes a conductive bump over the conductive pad. The conductive bump has a first portion, a second portion, and a neck portion between the first portion and the second portion. The first portion is between the neck portion and the conductive pad. The neck portion is narrower than the first portion and narrower than the second portion.

Chip package structure, chip structure and method for forming chip structure

A chip package structure is provided. The chip package structure includes a first chip structure including a substrate and an interconnect layer over the substrate. The chip package structure includes a second chip structure over the interconnect layer. The chip package structure includes a first conductive bump connected between the interconnect layer and the second chip structure. The chip package structure includes a conductive pillar over the interconnect layer. The chip package structure includes a molding layer over the interconnect layer and surrounding the second chip structure, the first conductive bump, and the conductive pillar. The chip package structure includes a second conductive bump over a first surface of the conductive pillar. The first surface faces away from the first chip structure.

A semiconductor structure includes a substrate comprising a die pad disposed over the substrate, and a passivation disposed over the substrate and surrounding the die pad, a redistribution layer (RDL) comprising a dielectric layer disposed over the passivation and an interconnect structure disposed within the dielectric layer and electrically connecting with the die pad, a conductive bump disposed over and electrically connected with the interconnect structure; and an isolation layer surrounding the substrate and the RDL.

Semiconductor structure and manufacturing method thereof

Growing community of inventors

Tai-Chung, Taiwan

Pei-Haw Tsao