Taiwan Semiconductor Manufacturing Comp. Ltd.

Pei-Chun Liao

Jian-Hong Lin

Yung-Huei Lee

Chun-Wei Chang

Chia-Lin Chen

Chin-Yuan Ko

Chih-Hung Nien

Wen-Hsien Kuo

Yu-Ming Lin

Yih Wang

Yi-Ching Liu

Chieh Lee

Yung-Sheng Tsai

Dawei Heh

Sheng-Hui Liang

Yu-Kai Chang

Wenhsien Kuo

A phase-change memory (PCM) cell is provided to include a first electrode, a second electrode, and a phase-change feature disposed between the first electrode and the second electrode. The phase-change feature is configured to change its data state based on a write operation performed on the PCM cell. The write operation includes a reset stage and a set stage. In the reset stage, a plurality of reset current pulses are applied to the PCM cell, and the reset current pulses have increasing current amplitudes. In the set stage, a plurality of set current pulses are applied to the PCM cell, and the set current pulses exhibit an increasing trend in current amplitude. The current amplitudes of the set current pulses are smaller than those of the reset current pulses.

Phase-change memory cell and method for fabricating the same

A memory device is provided, including a memory array, a driver circuit, and recover circuit. The memory array includes multiple memory cells. Each memory cell is coupled to a control line, a data line, and a source line and, during a normal operation, is configured to receive first and second voltage signals. The driver circuit is configured to output at least one of the first voltage signal or the second voltage signal to the memory cells. The recover circuit is configured to output, during a recover operation, a third voltage signal, through the driver circuit to at least one of the memory cells. The third voltage signal is configured to have a first voltage level that is higher than a highest level of the first voltage signal or the second voltage signal, or lower than a lowest level of the first voltage signal or the second voltage signal.

Memory device and method for operating the same

Disclosed herein are related to a system and a method of extending a lifetime of a memory cell. In one aspect, a memory controller applies a first pulse having a first amplitude to the memory cell to write input data to the memory cell. In one aspect, the memory controller applies a second pulse having a second amplitude larger than the first amplitude to the memory cell to extend a lifetime of the memory cell. The memory cell may include a resistive memory device or a phase change random access memory device. In one aspect, the memory controller applies the second pulse to the memory cell to repair the memory cell in response to determining that the memory cell has failed. In one aspect, the memory controller periodically applies the second pulse to the memory cell to extend the lifetime of the memory cell before the memory cell fails.

System and method for extending lifetime of memory device

The current invention provides a method of determining the lifetime of a semiconductor device due to time dependent dielectric breakdown (TDDB). This method includes providing a plurality of samples of dielectric layer disposed as a gate dielectric layer of a MOS transistor, approximating a source/drain current density distribution as a first function of voltage applied on the samples, approximating a substrate current density distribution as a second function of voltage applied on the samples, approximating a dielectric layer lifetime distribution as a third function of source/drain current density and substrate current density in the samples, deriving, from the first, the second, and the third functions, an empirical model wherein a dielectric layer lifetime is a function of voltage applied thereon, and using the model to determine dielectric layer lifetime at a pre-determined operating gate voltage.

Method for determining time dependent dielectric breakdown

A method for testing a batch of semiconductor devices in wafer level is provided. The method includes the following steps: (a) obtaining a breakdown voltage of gate dielectric of each semiconductor device; (b) applying, to the gate dielectric of each semiconductor device, a stress voltage below the breakdown voltage but above a base voltage of gate dielectric of the semiconductor devices; (c) after the step (b), measuring currents of gate dielectric of each semiconductor devices at the base voltage; and (d) obtaining a tailing distribution from the measured currents.

Method for testing semiconductor devices

An electroless plating apparatus is provided. The electroless plating apparatus includes a wafer holder; a chemical dispensing nozzle over the wafer holder; a conduit connected to the chemical dispensing nozzle; and a radiation source over the wafer holder.

One time programming memory cell using MOS device

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Jhubei, Taiwan

Pei-Chun Liao