International Business Machines Corporation

Globalfoundries Inc.

Pawel Owczarczyk

Alan J Drake

Michael Sperling

Xiaobin Yuan

Marshall Dale Tiner

Akil Khamisi Sutton

Erik English

Michael Stephen Floyd

David T Hui

Gregory Scott Still

Francesco A Campisano

Christian Jacobi

Chung-Lung K Shum

Alper Buyuktosunoglu

Anthony Saporito

William Vincent Huott

Adam B Collura

Tobias Webel

Michael J Cadigan, Jr

Stefan Payer

Paul David Muench

Christos Vezyrtzis

Chad Andrew Marquart

Sean Michael Carey

Douglas J Malone

Miguel E Perez

Paul Jacob Logsdon

Karl Evan Smock Anderson

Michael Romain

Mark Cichanowski

The method and systems described herein provide for identifying and mitigating undesirable power or voltage fluctuations in regions of a semiconductor device. For example, embodiments include detecting a region, such as an individual processor, of a processor chip is exhibiting a reduced power draw and a resulting localized voltage spike (e.g., a spike that exceeds Vmax) that would accelerate overall device end-of-life (EOL). The described systems respond by activating circuits or current generators located in the given region to draw additional power via a protective current. The protective current lowers the local voltages spikes back to within some pre-specified range (e.g., below a Vmax). The resulting reduction in the time above Vmax in testing reduces the number of devices that will need to be discarded due to Vmax violations as well as increases the expected reliability and lifespan of the device in operation.

Method to limit the time a semiconductor device operates above a maximum operating voltage

Aspects of the invention include forming a semiconductor device. Gates are formed in a first direction over fins, the gates including gate material, the fins being formed in a second direction. Fin interconnects are formed in the first direction over the fins. A dielectric material is formed on the fins, and capacitor interconnects are formed over portions of the dielectric material in the first direction over the fins.

FEOL interconnect used as capacitance over fins instead of gates

Aspects of the invention include a first voltage sensitive circuit including first transistors, the first transistors being coupled together so as to be operatively coupled to a first current source. A second voltage sensitive circuit includes second transistors, the second transistors being coupled together so as to be operatively coupled to a second current source, the first voltage sensitive circuit being coupled to the second voltage sensitive circuit to form a delay chain, the first and second current sources being responsive to changes in voltage of a power supply according to a voltage reference. A voltage sensitive current reference module is coupled to the first and second current sources and configured to supply the voltage reference to the first and second current sources, the voltage sensitive current reference module being responsive to changes in the voltage of the power supply.

Voltage sensitive current circuit

Aspects of the invention include a circuit having a power supply sensitive delay circuit, a variable delay circuit coupled to the power supply sensitive delay circuit, a delay line coupled to the variable delay circuit, and a logic circuit coupled to the delay line.

Droop detection using power supply sensitive delay

Aspects of the invention relate to an apparatus having a transmission gate coupled to a delay element and including a first transistor and a second transistor. A first node is coupled to a first gate of the first transistor, a first current source, and a first resistive element, an opposite end of the first resistive element being coupled to a ground potential. A second node is coupled to a second gate of the second transistor, a second current source, and a second resistive element, an opposite end of the second resistive element being coupled to a power supply.

Voltage starved passgate with IR drop

Aspects of the invention include a process for receiving data and a first clock signal of a first chip and a second clock signal of a second chip, the data being received on a data path and the first clock signal being received on a clock signal path, and determining that the first clock signal is arriving before the second clock signal by a difference quantity. Also, the process includes adding delay to the data path and the clock signal path according to the difference quantity.

Early mode protection for chip-to-chip synchronous interfaces

Aspects of the invention include a circuit including a power circuit having an amplifier, a resistor, a current source, and a first node, one end of the resistor being configured to couple to a power supply, the first node being coupled to an opposite end of the resistor, a first input terminal of the amplifier, and the current source. A voltage sensitive circuit includes a logic gate coupled to both a second input terminal of the amplifier and an output terminal of the amplifier at a second node.

Voltage sensitive delay

A technique relates to a digital phase locked loop (DPLL) including a digitally controlled oscillator (DCO), the DCO having delay elements and a current fill factor corresponding to a proportion of the delay elements in operation. A voltage regulator controller is operable to obtain a result of a comparison between a predefined fill factor and the current fill factor, the voltage regulator controller being operable to adjust voltage supplied to the DCO based on the result, the predefined fill factor indicating a predetermined proportion of the delay elements to be in operation.

Maintaining a digitally controlled oscillator at an ideal state by changing the voltage supply

According to one or more embodiments, a method implemented by a digital phase-locked loop of a processor is provided. The method includes turning off, by the digital phase-locked loop, a percentage of active devices of a digitally controlled oscillator to implement a fast path within the digital phase-locked loop. The method also includes reducing, by the digital phase-locked loop, a multiplier of a frequency filter setting to implement a control path within the digital phase-locked loop.

Programable immediate frequency change for digital phase locked loop

The present invention provides a system and method of increasing the resolution of on-chip timing uncertainty measurements. In an embodiment, the system includes a set of delay circuits logically coupled in a chain configuration, a plurality of flip-flop circuits logically coupled to the delay output of the each of the delay circuits respectively, forming tiers of flip-flop circuits, a clock circuit logically coupled to each of the tiers of flip-flop circuits respectively, and where the plurality of flip-flop circuits is logically configured, in response to a delay input of a first delay circuit in the set of delay circuits receiving an output from a programmable delay circuit and in response to receiving skewed clock signals from the clock circuits, to indicate how far within the plurality of flip-flop circuits an edge signal transmitted from the delay output of the each of the delay circuits propagated, respectively.

Increasing resolution of on-chip timing uncertainty measurements

An approach is provided in which a multi-core processor's first core determines whether it controls a system frequency that drives a group of cores included in the multi-core processor. When the first core is not controlling the system frequency for the group of cores, the first core uses an internal voltage control module to provide control information to the first core's programmable voltage regulator and, in turn, independently control the first core's voltage level. When the first core is controlling the system frequency, the first core receives voltage control information from pervasive control to control the first core's voltage levels.

Multi-core dynamic frequency control system

A computing circuit that includes clocked circuitry, a controller, and a clock generator. The clocked circuitry is configured to receive data and to perform data manipulation on the data based on a first clock signal. The controller is configured to control the transmission of the data to the clocked circuitry. The clock generator is configured to receive as inputs a second clock signal and a delay control signal from the controller, and to delay the second clock signal to generate the first clock signal. The clock generator includes a main delay component configured to receive the second clock signal and to output the first clock signal. The clock generator also includes a switchable delay component connected in parallel with the main delay component, where the switchable delay component is configured to receive as an input the delay control signal from the controller.

Programmable delay circuit

A critical path monitor (CPM) having a set of split paths is configured in an integrated circuit (IC) that includes a corresponding set of critical paths. A first and a second split path is configured with a first and a second simulated delay sections and fine delay sections, respectively. A delay of each of the first and second fine delay sections is adjustable in several steps. The delay of the first fine delay section is adjustable differently from the delay of the second fine delay section in response to a common operating condition change. Differently adjusting the delays of the first and the second fine delay sections causes an edge of a pulse to be synchronized between a first edge detector located after the first simulated delay section and a second edge detector located after the second simulated delay section.

Adjustable delay calibration in a critical path monitor

A circuit for monitoring and controlling a clock signal generated by a clock source in a microprocessor device may include a voltage divider network that provides a plurality of voltages, a selector device that receives the plurality of voltages and provides a scaled supply voltage and a scaled ground voltage from the plurality of voltages, and at least one delay element that receives the scaled supply voltage and the scaled ground voltage and generates a delayed pulse signal by applying a delay to each pulse of the clock signal. The delayed pulse signal may include a delay magnitude that is controllable by the scaled supply voltage and the scaled ground voltage, such that the delayed pulse signal is used to generate a frequency correction signal based on a variation to a supply voltage of the microprocessor. The frequency correction signal may then be applied to the clock source.

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Highland, NY, United States of America

Pawel Owczarczyk