International Business Machines Corporation

Globalfoundries Inc.

Intermec IP Corporation

Paul William Coteus

Todd Edward Takken

Gareth Geoffrey Hougham

Evan G Colgan

Alan G Gara

Brian Samuel Beaman

Stefano Sergio Oggioni

Enrique Vargas

Dong Chen

Philip Heidelberger

Shawn Anthony Hall

Thomas Mario Cipolla

Kyu-hyoun Kim

Matthias Augustin Blumrich

Mark Edwin Giampapa

Warren Edward Maule

Kevin Charles Gower

Shurong Tian

Daniel Mark Dreps

Martin Ohmacht

Andrew Ferencz

Pavlos Michael Vranas

Alphonso Philip Lanzetta

Hillery C Hunter

Robert Brett Tremaine

Charles Arthur Kilmer

Mark Delorman Schultz

Xin Zhang

Kerry Bernstein

Philip George Emma

Lawrence Shungwei Mok

Burkhard Steinmacher-Burow

Valentina Salapura

Frank David Ferraiolo

Luis Alfonso Lastras-Montano

Thomas M Gooding

Barry Marshall Trager

Dong Chen Chen

Paul Andrew Moskowitz

Ruchir Puri

Steven Alan Cordes

Chen-Yong Cher

Mark B Ritter

Daniel Peter Morris

Fuad Elias Doany

Kenneth Lee Wright

Mark Gregory Megerian

Michael K Gschwind

Michael A Gaynes

John Edward Sheets, Ii

Toshiaki Kirihata

Michael A Blocksome

William Louis Brodsky

Daniel Joseph Friedman

Eren Kursun

John Peter Karidis

Joseph D Ratterman

Adam James Muff

David Paul Paulsen

Robert H Dennard

Stephen Victor Kosonocky

Frank Robert Libsch

Bruce Martin Fleischer

Alexandre E Eichenberger

Robert L Wisnieff

Robert William Wisniewski

John A Gunnels

Kathryn Mary O'Brien

Michael John Brady

Sameh W Asaad

John Kevin O'Brien

Thomas Winters Fox

Peng Wu

Steven Paul Ostrander

Douglas James Joseph

Albert M Young

Yoonho Park

Charles David Wait

Allan Mark Hartstein

Jeannine Madelyn Trewhella

Sameer Kumar

Glen Arthur Wiedemeier

Brian E Smith

Patrick James Meaney

Leland Chang

Alejandro Gabriel Schrott

Russell Alan Budd

James Peter Ward

John G Torok

Robert J Von Gutfeld

Timothy Jay Dell

William Paul Hovis

Alfred Viehbeck

James A O'Connor

Mark William Kellogg

Edward Joseph Seminaro

Mark James Jeanson

Dah-Weih Duan

Brian Richard Sundlof

Theron Lee Lewis

An assembled circuit board has a topology that defines positions, dimensions and power dissipation of components mounted to the circuit board, including a high power component and one or more low power components. A cold plate makes thermal contact to the high power component through a thermal interface material. A thermally conductive sheet overlays the circuit board and is formed to match the topology of the low power component or components. The sheet has a first portion that makes thermal contact with the cold plate and a second portion that overlays the low power component or components. The cold plate removes heat directly from the high power component and indirectly through the thermally conductive sheet from the low power component or components. The thermally conductive sheet conforms to the topology of the low power components either by preforming or by flexibility.

Mechanically flexible cold plates for low power components

A card, e.g. a printed circuit board (PCB), has one or more conductive layers and one or more non-conductive layers disposed and alternating upon one another to form a stack. One or more of the conductive layers has one or more wiring elements within the conductive layer. The PCB/card has one or more card edges. The PCB also has a plurality of dual-level pad structures on each of one or more of the card edges. The dual-level pad structures each have an upper level, a lower level, and two or more walls. The lower level is a conductive pad with conductive surface. At least one of the conductive pads electrically connects to one or more of the wiring elements and/or one or more vias. In each of the dual-level pad structures, the walls and upper level may be made of an electrically non-conductive, insulating, or dielectric material or may be covered with a conductive material that electrically connects to conductive surface. There are different non-limiting embodiments of the structures and methods of making the structures.

Dual-level pad card edge self-guide and alignment of connector

An application to run on a hardware processor comprising a plurality of cores may be received. Hardware resource utilization data associated with the application may be obtained. A trained neural network with the hardware resource utilization data associated with the application is run, the trained neural network predicting core temperature associated with running the application on a core of the hardware processor. Based on the core temperature predicted by the trained neural network, the plurality of cores may be controlled to run selective tasks associated with the application.

Learning-based thermal estimation in multicore architecture

A switch-connected dragonfly network and method of operating. A plurality of groups of row switches is organized according to multiple rows and columns, each row including multiple groups of row switches connected to form a two-level dragonfly network. A plurality of column switches interconnect groups of row switches along respective columns, a column switch associated with a corresponding group of row switches in a row. A switch port with a same logical port on a row switch at a same location in each group along the respective column connects to a same column switch. The switch-connected dragonfly network is expandable by adding additional rows, an added row comprising a two-level dragonfly network. A switch group of said added row associated with a column being connects to an available port at an existing column switch of said column by corresponding added S path link with no re-cabling of the switched network required.

Switch-connected Dragonfly network

Voltage on the output terminal of an inductor is obtained as a first input signal to a control block (CB); the inductor has an input terminal connected to a power switch and driver block at a switching node. A sense input voltage is obtained on an output terminal of a sensing circuit that is not directly connected to the switching node, as a second input signal to the CB. A voltage is generated on a first output terminal of the CB and is selected such that the CB can use its first and second input signals to infer the current through the inductor. A pulse width modulation (PWM) signal is generated on a second output terminal of the CB, based on the inferred current through the inductor; the second output signal from the CB is provided to a PWM input terminal of the power switch and driver block.

Smart controller with phantom inductor current sensing for switched mode power supplies

An method for forming a cooling apparatus for cooling an electronic component. The apparatus has a planar top member of a thermal energy conductive material and a parallel planar bottom member of the material, the planar bottom member including a surface having regions configured for heat exchange contact with the electronic component. The planar top member has a plurality of stamped indent formations at a plurality of locations, each indent formation providing a contact surface such that the planar top member is affixed to the bottom member by braze or solder at each contact surface. Alternatively, the planar bottom member also has a plurality of stamped indent formations in alignment with indent formations of the top member. The planar top member is affixed to the bottom member by brazing or soldering each respective contact surface of an indent formation of the planar top member to an opposing contact surface of a corresponding indent formation of the parallel planar bottom member.

Burst resistant thin wall heat sink

A method for fabricating a semiconductor device includes, for a substrate having a first region protected by a cap layer, forming a first device on a second region of the substrate. The substrate includes an insulator layer disposed between a first semiconductor layer and a second semiconductor layer each including a first semiconductor material. The method further includes forming a second device on the first region, including forming one or more transistors each having a channel formed from a second semiconductor material different from the first semiconductor material.

High switching frequency, low loss and small form factor fully integrated power stage

An apparatus is provided including a transformer including a first printed circuit board having one or more conducting layers, the one or more conducting layers forming, at least in part, a transformer coil; at least one inductor; and at least one continuous piece of conducting material external to the printed circuit board, where the at least one continuous piece of conducting material forms a connection between the transformer and the at least one inductor. A method is also provided for assembling a switched-mode power supply.

Unified conductor to lower the resistance between a planar transformer and one or more inductors

An electrical connector carries large amounts of electrical current between two circuit boards with low resistance and low self-inductance by means of an interdigitated anode and cathode, thereby providing low dynamic voltage loss. The connector also may include, near where power will be consumed, an interposer board with on-board capacitance to provide even lower dynamic voltage loss. The connector has application to delivering low-voltage, high-current power from a power supply on a first board to electronics on a second board: the low resistance provides low voltage drop for a load current that is constant, while the low inductance and the capacitors provide low voltage fluctuation for a load current that changes. These issues are of great importance, for example, in designing high-performance computers.

Interdigitated power connector

A first method includes determining a total length of pending packets for a network link, determining a currently preferred power mode for the network link based on the total length of pending packets for the network link, and changing a current power mode for the network link to the currently preferred power mode. A corresponding apparatus is also disclosed herein. A second method includes determining a utilization for a network link, determining a currently preferred power mode for the network link based on the utilization for the network link, and changing a current power mode for the network link to the currently preferred power mode. A corresponding apparatus is also disclosed herein.

Power management of network links

A structure for a network switch. The network switch may include a plurality of spine chips arranged on a plurality of spine cards, where one or more spine chips are located on each spine card; and a plurality of leaf chips arranged on a plurality of leaf cards, wherein one or more leaf chips are located on each leaf card, where each spine card is connected to every leaf chip and the plurality of spine chips are surrounded on at least two sides by leaf cards.

High-density, fail-in-place switches for computer and data networks

Embodiments of the invention provide a method, system and computer program product for embedding a global barrier and global interrupt network in a parallel computer system organized as a torus network. The computer system includes a multitude of nodes. In one embodiment, the method comprises taking inputs from a set of receivers of the nodes, dividing the inputs from the receivers into a plurality of classes, combining the inputs of each of the classes to obtain a result, and sending said result to a set of senders of the nodes. Embodiments of the invention provide a method, system and computer program product for embedding a collective network in a parallel computer system organized as a torus network. In one embodiment, the method comprises adding to a torus network a central collective logic to route messages among at least a group of nodes in a tree structure.

Embedding global barrier and collective in a torus network

An embodiment includes a method for use in operating a memory chip, the method comprising: operating the memory chip with an increased burst length relative to a standard burst length of the memory chip; and using the increased burst length to access metadata during a given operation of the memory chip. Another embodiment includes a memory module, comprising a plurality of memory chips, each memory chip being operable with an increased burst length relative to a standard burst length of the memory chip, the increased burst length being used to access metadata during a given operation of the memory module.

Error correction potency improvement via added burst beats in a dram access cycle

Printed circuit board (PCB), electrical structures including PCBs, and methods for making the same. One PCB structures includes: a substrate having a plurality of surfaces, including a first aerial main face (AMF), a second AMF, and a first peripheral end face (PEF), wherein the first PEF separates the first AMF from the second AMF, and a first plurality of contacts embedded in the first PEF, where each of the first plurality of contacts forms a contiguous contact with the first PEF and at least one of i) the second AMF, ii) the first AMF, and iii) another one of the plurality of surfaces.

Electrical contacts on the sidewall of a circuit board

Growing community of inventors

Yorktown Heights, NY, United States of America

Paul William Coteus