Infineon Technologies Ag

Other

Paul Wensley

Martin Commons

Tobias Mono

Babar Ali Khan

David M Dobuzinsky

Chienfan Yu

Joyce C Liu

Thomas Schafbauer

Mohammed Fazil Fayaz

Veit Klee

Chuan Lin

John Pohl

Velt Klee

A memory device and method of manufacturing thereof, wherein a silicide material is selectively formed over active regions of a memory device. A silicide material may also be formed on the top surface of wordlines adjacent the active regions during the selective silicidation process. A single nitride insulating layer is used, and portions of the workpiece are covered with photoresist during the formation of the silicide material.

Selective silicidation scheme for memory devices

A method of providing shallow trench ( ) isolation for a semiconductor wafer ( ). Trenches ( ) are formed within a first semiconductor material ( ) and a pad nitride ( ), leaving a portion of first semiconductor material ( ) and pad nitride ( ) in a region between the trenches ( ). A second semiconductor material ( ) is deposited over the trenches ( ) to fill the trenches ( ) to a height below the first semiconductor material ( ) top surface. A first insulator ( ) is selectively formed over the second semiconductor material ( ). The pad nitride ( ) and a portion of the first semiconductor material ( ) between the trenches ( ) are removed to isolate element regions of the wafer ( ) and form straps ( ) having a low resistance.

Strap resistance using selective oxidation to cap DT poly before STI etch

A method of fabricating an integrated circuit chip having a first region of a first layout rule and a second region of a second layout rule. The method includes using a first material to establish a first hard mask pattern in only the first region and using a second material to establish a second hard mask pattern on top of the first hard mask pattern. The second material is additionally used to establish a third hard mask pattern in the second region.

Dual layer hard mask for eDRAM gate etch process

A method (see e.g., FIG. ) of fabricating a semiconductor device includes forming a trench in a semiconductor body . A dielectric layer is formed within the trench . Dielectric layer lines the sidewall and, possibly, the bottom portions of the trench in a manner where the thickness of the dielectric at the sidewall is greater than the thickness of the dielectric at the bottom. A dopant can then be implanted into the semiconductor body beneath the trench.

Method and structure for shallow trench isolation

Method of measuring combined critical dimension and overlay in single step

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Poughquag, NY, United States of America

Paul Wensley