Winbond Electronics Corporation

Hewlett-Packard Development Company, L.p.

Nuvoton Technology Corporation

Paul Vande Voorde

Chun-Mai Liu

Bal S Sandhu

Joseph Ku

Chang-Xian Wu

A floating-node memory device includes a metal-oxide-semiconductor (MOS) transistor including a first polysilicon gate, a source region, and a drain region in a first well region, a tunneling device including a second polysilicon gate in a second well region, and a metal-insulator-metal (MIM) capacitor including a conductive top plate and a bottom plate formed in a metal interconnect layer. The floating-node device includes a floating-node comprising the first polysilicon gate, the second polysilicon gate, and the conductive top plate of the MIM capacitor coupled together, a control node at the bottom plate of the MIM capacitor, an erase node in the second well region, a source node at the source region of the MOS transistor, and a drain node at the drain region of the MOS transistor.

Method and apparatus for analog floating gate memory cell

Ion implanted resistors formed in the body of a crystalline silicon substrate. The resistors have a different conductivity type from that of the silicon substrate. The sheet resistance and temperature dependence of the resistor layer is determined by the dose of the implant. Temperature variation can be optimized to be less than 2% over the temperature range &#x2212;40 C to +85 C. Furthermore, the temperature variation at room temperature (&#x2dc;25 C) can be reduced to nearly zero.

Semiconductor diffused resistors with optimized temperature dependence

The apparatus and method for forming de-coupling capacitors on top of SOC VLSI chip. The introduced large amount of de-coupling capacitor is intended to solve the power delivery problem of highly integrated and powered VLSI chip, especially in the Silicon-On-Insulator (SOI) technology. This invention proposes a design scheme which could utilize virtually unused area to build efficient de-coupling capacitors without introducing additional manufacture cost. This design scheme is especially effective when the VLSI technology is scaled down further.

Method and apparatus for building up large scale on chip de-coupling capacitor on standard CMOS/SOI technology

Ion implanted resistors formed in the body of a crystalline silicon substrate. The resistors have a different conductivity type from that of the silicon substrate. The sheet resistance and temperature dependence of the resistor layer is determined by the dose of the implant. Temperature variation can be optimized to be less than 2% over the temperature range &minus;40 C to &plus;85 C. Furthermore, the temperature variation at room temperature (&tilde;25 C) can be reduced to nearly zero.

Growing community of inventors

San Mateo, CA, United States of America

Paul Vande Voorde