Motorola Corporation

Other

Paul T Lin

Michael B McShane

Howard P Wilson

Charles G Bigler

John A Goertz

Bich-Yen Nguyen

Philip J Tobin

Israel A Lesk

James J Casto

James W Sloan

Roger S Countryman, Jr

Jonathan C Dahm

Chi-Shih Chang

John G Franka

Young Limb

Gary L Huffman

Takehi Sato

Sugio Uchida

Joan M Hamilton

Cap with changeable brim and snap fastener covers

The present invention discloses an electronic package to contain and protect an integrated circuit (IC) chip. The electronic package further includes a leadframe, a flexible circuit or PCB type of substrate. The leadframe, flexible circuit or PCB type substrate further includes solder contacts, which are aligned with via holes in the molding layers on the top and bottom sides of the package. These via holes are for placing solder paste or solder balls from above and below for electrical access to the IC chip. These solder balls provide access for electrical testing after the package is mounted on a motherboard. They also provide the connection points for stacking multiple packages vertically.

Package with solder-filled via holes in molding layers

The present invention includes a chip-embedded support-frame wrapped-by-flex-circuit package assembly. The package assembly includes a flex circuit having a plurality of patterned connecting-traces. The package assembly further includes a plurality of semiconductor chips mounted on the flex circuits wherein the semiconductor chips having a plurality of contact terminals connected to corresponding connecting traces on the flex circuit. The package assembly further includes a support frame-board having an edge surface placed along predefined folded lines on the flex circuit. The frame-board has a plurality of open spaces for disposing each of the semiconductor chips therein. The flex circuit is provided for folding onto the support frame along the predefined folded lines to form the chip-embedded support-frame wrapped-by-flex-circuit package.

Chip-embedded support-frame board wrapped by folded flexible circuit for multiplying packing density

A semiconductor die (14) is mounted over a power supply surface (24, 52, 62). Signal bonding pads (18) on the die are wire bonded to corresponding leads (38) of a leadframe. Power supply bonding pads (20, 21) on the die are wire bonded to the power supply surface. A package body (22, 42, 56) surrounds the semiconductor die, the wire bonds (32, 34, 40, 40'), and the power supply surface. The power supply pad terminals are accessible from the bottom of the package body of the device through a plurality of conductive apertures (28, 56) disposed in the lower half of the package body. Power supply solder bumps (12, 58) are connected to the power supply surface inside the package body through the conductive apertures. The leads are used provide input and out signals for the device around the periphery of the device, while the solder bumps are disposed in an array format on the package body.

Leaded semiconductor device having accessible power supply pad terminals

A ball grid array semiconductor device (10) includes a package substrate (14 or 16) having a plurality of conductive traces (18), bond posts (20), and conductive vias (22). A semiconductor die (12) is mounted to the package substrate. Orthogonal wire bonds (28) are used to electrically connect staggered bond pads (26) to corresponding bond posts (20) on the substrate. A liquid encapsulant (40) is used to cover the die, the wire bonds, and portions of the package substrate. In another embodiment, a package substrate (50) includes a lower bonding tier (52) and an upper bonding tier (54). Wire bonds (60) are used to electrically connect an outer row of bond pads (64) to bond posts (20) of lower tier (52), while wire bonds (62) are used to electrically connect an inner row of bond pads (64) to bond posts (20) of an upper tier (54). The loop height of wire bonds (60) is smaller than that of wire bonds (62).

Liquid encapsulated ball grid array semiconductor device with fine pitch

A thermally enhanced semiconductor device (10) having an exposed backside (22) is described. In one embodiment, a PC board substrate (12) is provided having a pattern of conductive traces (14) on both upper and lower surfaces of the substrate. Electrical continuity is maintained between the two surfaces with conductive vias (16). A semiconductor die (18) is flip-mounted to the upper surface of the substrate. Solder bumps (26) electrically connect the die to the conductive traces, and an underfill (28) couples the active side (20) of the die to the upper surface of the substrate. A package body (40) is formed around the perimeter (24) of the die leaving the inactive backside exposed for enhanced thermal dissipation. The inactive backside can also be coupled to a heat sink for increased thermal dissipation. A plurality of solder balls (42) electrically connected to the conductive traces is attached to the lower surface of the substrate.

Thermally enhanced semiconductor device having exposed backside and

A semiconductor (30) is shielded from electromagnetic interference by a combination of a reference plane (22) of a circuitized substrate (12) and two different encapsulants. The first encapsulant (38) is an electrically insulative encapsulant which mechanically protects a semiconductor die (32). The first encapsulant is constrained by a dam structure (40) so as not to encapsulate conductive reference pads (18) which are electrically connected to the reference plane by conductive vias (20). A second encapsulant (42) is dispensed over the first encapsulant and is in contact with the reference pads. The second encapsulant is an electrically conductive encapsulant, and is preferably made of a precursor material having the same or similar properties as that of the first encapsulant, but is filled with conductive filler particles to establish electrical conductivity of the encapsulant. Accordingly, the semiconductor die is effectively shielded from both the top and bottom by the electrically conductive encapsulant and the reference plane.

Shielded liquid encapsulated semiconductor device and method for making

A quad leadframe (22') for a CERQUAD is manufactured using conventional cladding and stamping technologies. A first metal layer (12) is provided with multiple cavities (14). A second metal layer (14) is clad to the first metal layer. A leadframe strip (22) can then be stamped from the clad metal. The leadframe has a leads (24) and bonding posts (28). The leads comprise two metal layers, and the bonding posts comprise only the second metal layer. The leadframe can then be used in the assembly of a semiconductor device (32). The portion of the leads external to the package body can be optionally etched to remove the second metal layer.

Method for making an aluminum clad leadframe and a semiconductor device

Semiconductor device employing an aluminum clad leadframe

An improved semiconductor device is disclosed having a predetermined amount of solder, or other electrically conductive binder adsorbed onto the exterior package leads of the semiconductor device. A de-wettable coating comprising preferably nickel, or alternatively chromium, is plated to a superior portion of the package leads, such that, when the heat is applied to the substrate mounting end of the leads, solder desorbes from the de-wettable layer and flows down the lead to the contact pads on the mounting substrate and forms a solder joint. The amount of solder delivered to the contact pad for joint formation is determined by the thickness of the adsorbed solder layer overlying each package lead. Only enough solder is provided on each lead sufficient to form the joint thus avoiding solder bridging between adjacent contact pads.

Surface mountable semiconductor device having self loaded solder joints

Contaminants are removed from a semiconductor material by heating the semiconductor material to temperature within the range of a minimum temperature where a halogen compound will decompose to halogen atoms without the use of ultraviolet irradiation and react with contaminants present on the semiconductor material and a maximum temperature of 800.degree. C., wherein less than or equal to approximately 50 Angstroms of oxide is formed on the semiconductor material. The ambient in which the semiconductor material is heated is an ambient comprised of a nonreactive gas and a halogen compound for at least a time sufficient to remove a substantial amount of contaminants from the semiconductor material.

Method of removing contaminants

A semiconductor multiple package module (10) on a PCB material substrate (18) is provided, wherein semiconductor dice are directly mounted onto the PCB material substrate (18) thereby eliminating a subsequent board mounting at the customer level. A plurality of semiconductor dice are mounted and electrically connected to a plurality of circuit traces (22) on the PCB material substrate (18) having a plurality of edge connectors (20). The plurality of circuit traces (22) has conductive paths to electrically interconnect the semiconductor dice to the edge connectors (20) and to each other. The semiconductor dice are directly overmolded on the PCB material substrate (18) with a molding compound to form individual semiconductor devices (12, 14, and 16) having separate package bodies. The individualized package bodies enable repair to the module by making removal of only nonfunctional semiconductor devices from the PCB material substrate (18) possible.

Repairable semiconductor multi-package module having individualized

A low cost manufacturing method is used to fabricate a small multichip semiconductor device (30). In one embodiment, a pattern of conductive traces (13) is formed on a film of transfer material (12). A first semiconductor die (15) is interconnected to the traces and a resin body (20) is formed around the first die and one side of the traces. The film of transfer material forms, at this stage of the process, one side of the first package. The film of transfer material is then peeled from the pattern of conductive traces and the first resin body to expose the other side of the traces. A second semiconductor die (23) is interconnected to the exposed side of the traces. A second resin body (25) is formed around the second die and portions of the exposed traces. Solder balls (26) are coupled to the exposed portions of the traces to establish external electrical connections to each die.

Method for attaching conductive traces to plural, stacked, encapsulated

A composite flip chip semiconductor device (10) permits burn-in testing and rework to be performed on the device while also enhancing electrical, thermal, and mechanical device performance. The device includes a semiconductor die (12) having a plurality of bonding pads (14). Also included in the composite device is an interposer (22) having a first surface with a plurality of traces (26). A plurality of vias (24) extend from the first surface of the interposer (22) to a second surface. The semiconductor die (12) is electrically coupled to the plurality of vias of the interposer which in turn is to be coupled to a substrate.

Composite flip chip semiconductor device with an interposer having test

A stackable three dimensional leadless multi-chip module (10) is provided whereby each level of semiconductor device (11) is interconnected to another level through reflowing of solder plated wires (22). Each semiconductor device (11) contains a semiconductor die (24) overmolded by a package body (12) on a PCB substrate (14) having a plurality of edge metal conductors (16) that form half-vias (18). The half-vias (18) at the edges of substrate (14) give the substrate a castellated appearance, where the castellations serve as the self-aligning feature during the stacking of the devices (11). Each device (11) is simply stacked on top of each other without any additional layers to give the semiconductor module (10) a lowest possible profile. A plurality of solder plated wires (22) fits into the half-vias (18) and is solder reflowed to the metal conductors (16) to interconnect the semiconductor devices (11). The wires (22) are bent to enable the module (10) to be surface mounted to a PC board.

Growing community of inventors

Austin, TX, United States of America

Paul T Lin