Olin Corporation

Advanced Interconnect Technologies Limited

International Business Machines Corporation

Cyrix Corporation

Paul R Hoffman

Deepak Mahulikar

Jeffrey S Braden

George A Brathwaite

German J Ramirez

Anthony M Pasqualoni

Dexin Liang

Derek E Tyler

Linda E Strauman

Paul Andrew Moskowitz

Timothy C Reiley

Mark B Ritter

Arvind Parthasarathi

James M Popplewell

Mark F Bregman

Peter G Ledermann

Markus K Liebhard

Roger Alan Pollak

Keshav B Prasad

Thomas Caulfield

Sean T Crowley

Michael A Holmes

Doanh D Bui

Salvador A Tostado

Sonny S Pareno

Richard McNabb

Francis S Jewell

Dawit Solomon

Peter W Robinson

Kambhampati Ramakrishna

Michael A Raftery

Serafin P Pedron, Jr

George A Erfe

There is provided an edge connectable electronic package. The package has a metallic base at least partially coated with a dielectric layer. An interconnection means taking the form of either a leadframe or a circuit trace is electrically interconnected to an encased semiconductor device. The opposing end of the interconnection means extends to the package perimeter for interconnection to a socket or brazing to external leads.

Edge connectable metal package

There is provided a ball grid array package for housing semiconductor devices. The package has a metallic base with conductive vias extending through holes formed in the base. The conductive vias terminate adjacent an exterior surface of the base. A dielectric coating on at least part of the base and through hole walls electrically isolates the metallic base from the package circuitry.

Ball grid array electronic package

The bending of a ball grid array electronic package having a metallic base is reduced minimizing stresses applied to the innermost row of solder balls when the package base is cyclically heated and cooled. Reducing the stresses applied to the solder balls increases the number of thermal cycles before solder ball fracture causes device failure. Among the means disclosed to reduce the bending moment are a bimetallic composite base, an integral stiffener, a centrally disposed cover bonded to an external structure and a package base with a stress accommodating depressed portion.

Metal ball grid electronic package having improved solder joint

A semiconductor package is provided that has a rigid metal substrate and a dielectric layer covering a first portion of the rigid metal substrate, with a second portion of the rigid metal substrate being substantially free of the dielectric layer. A semiconductor device is electrically bonded to the second portion of the rigid metal substrate and metal circuit traces defining electrical paths are formed on the dielectric layer, at least one of which contacts the rigid metal substrate through at least one via in the dielectric layer. Additionally, a method is provided for grounding a semiconductor device and at least one circuit trace on a rigid metal substrate substantially covered by a dielectric layer, which includes creating at least one via in the dielectric layer using a laser and creating circuit traces on the dielectric layer, at least one of which contacts the rigid metal substrate through at least one of the vias. The semiconductor is electrically bonded to the rigid metal substrate in an aperture in the dielectric layer.

Semiconductor package having a ground or power ring and a metal substrate

A surface mount package to encapsulate one or more semiconductor devices has a standoff that maintains the thickness of solder columns bonding the package to an external circuit. The standoff either extends over or circumscribes a central portion of the package base. To enhance the thermal performance of the standoff, a solderable layer enhances soldering of the standoff to the external circuit. In alternative embodiments, the standoff contains a flange having a plurality of apertures useful for either mechanically locking an adhesive or for enabling irradiation of an adhesive by a light source. The standoff may contain protrusions for alignment, strength or circuit routing.

Ball grid array electronic package standoff design

There is provided a component for an electronic package and a method for the manufacture of that component. The component has a metallic substrate with a surface coated by a dielectric. A centrally disposed cavity extends through the dielectric into the metallic substrate to a depth, D.sub.1. Circumscribing and abutting this cavity is an annular channel having a depth D.sub.2 that is less than D.sub.1. A semiconductor device bonded to the base of the cavity is electrically interconnected to both circuit traces formed on the dielectric coating and to the annular channel. A method of forming the annular channel is to mechanically mill a precursor annular channel having an outer wall a desired distance from the sidewalls of the metallic substrate and a width substantially greater than the desired width of the annular channel. A cavity is then formed in the region circumscribed by the outer wall of the precursor annular channel. The perimeter of this cavity approaches the outer wall of the precursor annular channel, terminating a desired distance from the outer wall such that that portion of the annular channel having a depth D.sub.2 is a desired width, typically less than 0.015 inch.

Ground ring for a metal electronic package

There is disclosed components for electronic packaging applications having integral bumps. A leadframe is formed by etching a metallic strip from one side to form outwardly extending, substantially perpendicular integral bumps. The metallic strip is then etched from the opposite side to form individual leads. When the integrally bumped component is an package base, fatigue of solder balls is reduced.

Metal ball grid array package with improved thermal conductivity

There is provided a metallic component for an electronic package. The component is coated with an electrically non-conductive layer and has a plurality of conductive circuit traces are formed on a surface. The circuit traces are soldered directly to the input/output pads of an integrated circuit device and to a second plurality of circuit traces. The component may include a heat sink to enhance dissipation of heat from an encapsulated integrated circuit device.

Components for housing an integrated circuit device

There is provided a leadframe having a plurality of coplanar electrically conductive leads. At least one metallic guard is bonded to the leads with a dielectric layer disposed between the metallic guard and the leads. The metallic guard has good adhesion to a polymer molding resin such that when the leadframe structure is encased in a molding resin, delamination is minimized. By restricting delamination, the ingress of water and water soluble contaminants to an integrated circuit device is inhibited.

Guard ring for integrated circuit package

There is provided a base for an electronic package. The base includes a peripheral portion for a polymer adhesive and a central portion for one or more semiconductor devices. A lead support is adjacent the substrate and located between the peripheral portion and the central portion. When a polymer adhesive bonds a leadframe to the package base, the lead support prevents deflection of the inner lead tips.

Electronic package having improved wire bonding capability

There are provided polymer plugs for sealing the vent hole of an adhesively sealed electronic package. The polymer vent hole plug is selected to be either an ultraviolet curable polymer or a thermosetting polymer resin. One effective vent hole plug is a cylindrical plug having a diameter under 1.4 millimeters formed from a UV-curable epoxy.

Polymer plug for electronic packages

There is disclosed an adhesively sealed electronic package in which a compensation apparatus is provided for excess adhesive. As a result, excess adhesive does not extend beyond the package perimeter, squeeze-out, or travel along the inner lead fingers interfering with wire bonding. The compensation is a chamfer on the peripheral edges and/or interior edges of the package base component and cover component.

Chamfered electronic package component

An electronic package with a semiconductor chip, a lead frame, a metal casing, and a redistribution interposer. The chip is mounted on the interposer and wirebonded to first ends of redistribution leads of the interposer. The redistribution leads have second ends orientated in a general flipped orientation relative to their corresponding first ends. The second ends are wirebonded to pads of the lead frame. The interposer allows smaller chips to be used in the package without changing the lead frame. The interposer also allows the chip to be flip-mounted in the package without changing the lead frame or casing, this allows redirection of the chip's thermal path.

Semiconductor package with chip redistribution interposer

There is provided an electronic package where the package components define a cavity. A semiconductor device and a portion of a leadframe occupy part of the cavity. Substantially the remainder of the cavity is filled with a compliant polymer, such as a silicone gel. Since the cavity is no longer susceptible to gross leak failure, the seal width of adhesives used to assemble the package may be reduced, thereby increasing the area available for mounting the semiconductor device.

Metal electronic package with reduced seal width

There is provided a module for supporting a plurality of semiconductor devices within an electronic package. The module has a support substrate and an apertured substrate laminated together with a polymer adhesive. A plurality of semiconductor devices are disposed within apertures formed in the apertured substrate and bonded to the support substrate by that same polymer adhesive.

Growing community of inventors

Modesto, CA, United States of America

Paul R Hoffman