Chartered Semiconductor Manufacturing Ltd (corporation)

Paul Proctor

Subramanian Balakumar

Jia Zhen Zheng

Yelehanka Ramachandramurthy Pradeep

Chew Hoe Ang

Chen Feng

Victor Seng-Keong Lim

Feng Chen

Chivukula Subrahmanyam

Seng-Keong Victor Lim

Robert Chin Fu Tsai

Zou Zheng

Zhou Mei Sheng

Mukhopadhyay Madhusudan

Victor Lim

Cheng-Hou Loh

An improved and new process of fabricating high dielectric constant MIM capacitors. These high dielectric constant MIM capacitor met all of the stringent requirements needed for both for both RF and analog circuit applications. For the high dielectric constant MIM capacitor, the metal is comprised of copper electrodes in a dual damascene process. The dielectric constant versus the total thickness of super lattices is controlled by the number of layers either 4/4, 2/2, and 1/1 artificial layers. Hence thickness of the film can be easily controlled. Enhancement of dielectric constant is because of interface. Dielectric constants near 900 can be easily achieved for 250 Angstrom thick super lattices. MBE, molecular beam epitaxy or ALCVD, atomic layer CVD techniques is used for this type layer growth process.

High K artificial lattices for capacitor applications to use in Cu or Al BEOL

A polish apparatus for planarizing wafers and films over wafers comprising the following. A substrate chuck for holding a substrate with a surface to be polished thereof being directed about vertically. A first drive means for rotating the substrate chuck. A polishing head having a polishing surface which is adjacent to the substrate during the polishing of the substrate. The polishing surface of the polishing head is smaller than the surface of the substrate. A polishing solution supply means for supplying a polishing solution through the polishing head to the substrate held by the substrate chuck. A reciprocating means for reciprocally moving the polishing head on the surface to be polished. A pressing means for pressing the polishing pad against a substrate held by the substrate chuck by way of the polishing head. The polish head is preferably comprised of one piece of molded polymer. No polish pad is used.

Chemical-mechanical polisher hardware design

A process of fabricating high dielectric constant MIM capacitors. The high dielectric constant MIM capacitors are for both RF and analog circuit applications. For the high dielectric constant MIM capacitors, the metal is comprised of copper electrodes in a dual damascene process. The dielectric constant versus the total thickness of super lattices is controlled by the number of artificial layers. Dielectric constants near 900 can be achieved for 250 Angstrom thick super lattices. MBE, molecular beam epitaxy or ALCVD, atomic layer CVD techniques are employed for the layer growth processes.

High K artificial lattices for capacitor applications to use in CU or AL BEOL

A linear polishing apparatus for polishing a semiconductor substrate including a novel polishing belt arrangement with at least two polishing belts forming a continuous loop. Each belt having an outside polishing surface and an inside smooth surface. The belts are spaced alongside each other sharing a common axis at each end. The belts are looped around a pair of rollers making up a driver roller at one end and a driven roller at the other end. A platen member interposes each belt and is placed between the pairs of rollers. The platen provides a polishing plane and supporting surface for the polishing belts. The polishing plane includes a plurality of holes communicating with an elongated plenum chamber underlying the plane. The chamber supplies a compressed gas to impart an upward pressure against the polishing belts. The driver rollers are coupled to separate motors to independently drive and control at least said two of the polishing belts.

Linear polishing for improving substrate uniformity

A new method is provided for the creation of STI regions. STI trenches are created in the surface of a substrate following conventional processing. A layer of STI oxide is deposited and, using an exposure mask that is a reverse mask of the mask that is used to create the STI pattern, impurity implants are performed into the surface of the deposited layer of STI oxide. In view of these processing conditions, the layer of STI oxide overlying the patterned layer of etch stop material is exposed to the impurity implants. This exposure alters the etch characteristics of the deposited layer of STI oxide where this STI oxide overlies the patterned layer of etch stop material. The etch rate of the impurity exposed STI oxide is increased by the impurity implantation, resulting in an etch overlying the patterned etch stop layer that proceeds considerably faster than the etch of the STI oxide that is deposited overlying the created STI trenches. With the significantly faster etch of the STI oxide where this oxide has been exposed to impurity implantation, the STI oxide removal can be equalized between the STI oxide that overlies the patterned etch stop layer and the oxide that has been deposited over the STI trenches.

STI scheme to prevent fox recess during pre-CMP HF dip

An improved chemical mechanical polishing apparatus for planarizing semiconductor surface materials. The single rotating polishing platen with an attached pad of conventional CMP processes is replaced with two controlled independently driven, concentric and coplanar, polishing platens. The two co-planar polishing platens allows for separate adjustable options to the CMP polishing process. The options are provided by having pads of different material compositions and hardness. Moreover, an annular space is provided between the platens to introduce the usage of two slurry formulations, one to each pad, on the same CMP tool. The annular space between platens forming a drain path for catching and containing slurry waste.

Multiple step CMP polishing

A new method of forming shallow trench isolations using a reverse mask process is described. A polish stop layer is deposited on the surface of a substrate. An etch stop layer is deposited overlying the polish stop layer. A plurality of isolation trenches is etched through the etch stop layer and the polish stop layer into the substrate whereby narrow active areas and wide active areas of the substrate are left between the isolation trenches. An oxide layer is deposited over the etch stop layer and within the isolation trenches. The oxide layer is covered with a mask in the narrow active areas and in the isolation trenches and etched away in the wide active areas stopping at the etch stop layer. Thereafter, the mask is removed and the etch stop layer is polished away to the polish stop layer whereby the oxide layer in the isolation trenches is planarized.

Pre STI-CMP planarization scheme

A novel method to remove residual toxic gases trapped by a polymerizing process by an inert ion sputter is described. A masking layer is formed overlying a semiconductor substrate. An opening is etched through the masking layer into the semiconductor substrate whereby a polymer forms on sidewalls of the opening and whereby residual toxic gas reactants from gases used in the etching step are adsorbed by the polymer. Thereafter, the polymer is sputtered with non-reactive ions whereby the residual toxic gas reactants are desorbed from the polymer to complete removal of residual toxic gas reactants in the fabrication of an integrated circuit device.

Growing community of inventors

Singapore, Singapore

Paul Proctor