International Business Machines Corporation

Paul M Fahey

Devendra K Sadana

Herbert Lei Ho

Wilbur David Pricer

Gary Bela Bronner

Bernard S Meyerson

Thomas N Jackson

Erwin Hammerl

Craig M Ransom

Mutsuo Morikado

Joseph F Degelormo

A method of forming shallow trench isolation with a nitride liner layer for devices in integrated circuits solves a problem of recessing the nitride liner that led to unacceptable voids in the trench filler material by using a liner thickness of less than 5 nm. A densification step of a pyrogenic oxide anneal at 800.degree. C. not only drives out impurities and achieves the same density as a conventional argon anneal at 1000.degree. C., but also drastically reduces the thermal load.

Shallow trench isolation with thin nitride liner

A method is provided for diffusion doping of semiconductor chips and wafers, in particular silicon chips and wafers, at peak concentrations of greater than about 3.times.10.sup.19 atoms/cm.sup.3. The semiconducting material to be doped is placed in a furnace wherein the furnace contains an atmosphere of a carrier gas and a dopant containing gas. The doping containing gas is greater than about 0.1 volume percent of the total volume in the furnace chamber. The pressure of the composite gas is greater than about 0.1 Torr. The composite gas has an oxidizing agent concentration of less than about 1 part per million. The method permits the direct doping of a silicon surface to form a shallow n-doped region having a high peak concentration by a diffusion process thereby eliminating damage to the silicon surface from ion implantation which is the commonly used method to achieve these high doping concentrations. Since the method is nondirectional trench sidewalls can be doped at high concentrations.

Highly doped semiconductor material and method of fabrication thereof

A fabrication method for forming SOI structures where perfect material is grown epitaxially on a substrate and then, through a series of selective etches and oxidations, an insulating layer is formed below the epitaxial silicon. In the method, low temperature epitaxial techniques are employed to grow a layered structure including a first layer p++ silicon on a substrate wafer, a layer of intrinsic silicon is then formed on the first p++ silicon layer, and a second layer of p++ silicon is formed on the intrinsic silicon layer, and a finally a layer of p-silicon is fabricated on top of the second p++ silicon layer. Grooves are formed through the p-layer, the second p++ silicon layer, the intrinsic silicon layer, and stopped in the first p++ silicon layer. An etch is then employed to remove the intrinsic layer long enough for the p++ silicon layer to be totally undercut, leaving an air gap between the two p++ silicon layers. An oxidation step is then performed to form a bottom insulator consisting of the oxidized first p++ silicon layer and on an upper insulator consisting of the oxidized second p++ silicon layer.

Method for fabricating silicon-on-insulator structures

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Paul M Fahey