International Business Machines Corporation

Paul L Wiltgen

John E Campbell

Guy Richard Currier

Michael James Chan

Sharon Denos Vincent

Steven F Hajek

Steven Michael Douskey

John Robert Elliott

James Scott Harveland

James Maurice Wallin

Michael Charles Cogswell

Albert Tarolli

Nicholas P Hannon

Methods and apparatus are provided for connecting a manufacturing test interface to a global serial bus, such as an inter integrated circuit (I C) bus. Input/output buffer logic buffers data to be transferred to and from the global serial bus. A slave interface logic connected to the input/output buffer logic receives and sends data to the input/output buffer logic. A slave controller coupled to the input/output buffer logic and the slave interface logic paces data exchange to the input/output buffer logic. Error detection logic is coupled between the input/output buffer and the global serial bus for detecting error conditions.

Method and apparatus for connecting manufacturing test interface to a global serial bus including an I2 c bus

A data processing system, integrated circuit device, program product, and method thereof utilize a service interface to provide external access to a plurality of cores integrated into an integrated circuit device. The service interface, which may be utilized to perform external data transfer through a service access port in connection with a predetermined service operation, is separate from any function interface that is utilized during regular operation of the device. The service interface includes a plurality of core interface units integrated with selected cores on the device and coupled to the service access port through a master interface unit that is configured to request at least one of the core interface units to initiate execution of a predetermined service operation. As such, a multitude of service operations may be initiated in any number of the cores through a common service access port without occupying a large number of I/O pins and without necessitating interruption of the regular operation of the device.

Multi-core chip providing external core access with regular operation

A system is disclosed for selectively altering the functional characteristics of a data processing system without physical or mechanical manipulation by providing an access code from a remote personal identification number generator to a secure controller and store of the computer system. This enables remote authorization of change in function of the computer system, such as performance tune up, speeding clock time, changing function and like changes. The computer system is first manufactured having a predetermined set of functional characteristics. A multibit alterable code which includes a functional characteristic definition is then initially loaded into physically secure, nonvolatile memory within the data processing system, utilizing an existing bus, or a fusible link which may be opened after loading is complete. The functional characteristic definition is loaded from nonvolitile memory into a nonscannable register within a secure portion of a control logic circuit each time power is applied to the data processing system and the definition is then utilized to enable only selected functional characteristics. Alternate functional characteristics may thereafter be selectively enabled by entering a security code which matches one of a number of preloaded codes and an encoded alternate functional characteristic definition. The alternate functional characteristic definition may be enabled on a one-time, metered, or regularly scheduled basis and variable capability data processing systems may be implemented in this manner utilizing a single manufactured system, without the necessity of manufacturing and storing multiple data processing system models.

Self modifying access code for altering capabilities

A system and method of determining the propagation delay between LSSD (Level Sensitive Scan Delay) latch pairs is performed by modifying system and scan clock sequences. A set bit is initially scanned to the input of the sending trigger. This is done by inhibiting the last B clock. These A and B clocks are then gated off and the system clocks operate a complete cycle with the unique sequence of inhibiting the first latch pulse and the last trigger pulse. Finally, a unique scan clock sequence is used to scan out data from the receiving latch. If the data scanned out corresponds with expected data (the set bit), the process is repeated decreasing the cycle time of the system clocks until the set bit is no longer received. The measured delay is then taken as the preceding cycle time. By measuring the delays between a plurality of points and a common originating point and taking the differences in these delays, the skew in a clock distribution system can be readily determined.

System timing analysis by self-timing logic and clock paths

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Hurley, NY, United States of America

Paul L Wiltgen