Freescale Semiconductor,inc.

Nxp B.v.

Motorola Corporation

Nxp Usa, Inc.

Paul Grudowski

Venkat Kolagunta

Vance H Adams

Mehul D Shroff

Brian A Winstead

Olubunmi O Adetutu

Tab Allen Stephens

Kurt H Junker

Tien Ying Luo

Stefan Zollner

Sangwoo Lim

Veeraraghavan Dhandapani

Hsing H Tseng

Choh-Fei Yeap

Jian Feng Chen

Bich-Yen Nguyen

Perry H Pelley

Mark Douglas Hall

James David Burnett

Michael B McShane

Voon-Yew Thean

Da Zhang

Stanley Michael Filipiak

Gregory S Spencer

Matthew Thomas Herrick

Viet Thanh Dinh

Yeong-Jyh Tom Lii

Andrew G Nagy

Rana P Singh

Yongjoo Jeon

Srinivas Jallepalli

John J Hackenberg

Chad Weintraub

Mohamad M Jahanbani

Xiangzheng Bo

Geoffrey C-f Yeap

Marina Vroubel

Thomas J Kropewnicki

Darren V Goedeke

Darren V Goedekc

Yongloo Jeon

Viet Dinh

Stanley L Filipiak

Guido Sasse

Xiang-Zheng Bo

A semiconductor device is disclosed, a substrate structure; a raised source region; a raised drain region; a separation region disposed laterally between the raised source region and the raised drain region; a gate structure, disposed between the raised source region and the raised drain region and above a part of the separation region, the gate structure being spaced apart from the drain region and defining a drain extension region therebetween; a dummy gate structure in the drain extension region; an epitaxial layer, disposed above and in contact with the substrate structure and forming the raised source region, the raised drain region, and a raised region between the gate structure and the dummy gate structure, wherein the raised region between the gate structure and the dummy gate structure is relatively lightly doped to a conductivity of a second conductivity type which is opposite the first conductivity type.

Lateral semiconductor device having raised source and drain, and method of manufacture thererof

A semiconductor device comprising a pn junction diode and a method of making the same. The device includes a semiconductor substrate having a first conductivity type. The device also includes a buried oxide layer located in the substrate. The device further includes a semiconductor region having a second conductivity type extending beneath the buried oxide layer to form a pn junction with a semiconductor region having the first conductivity type. The pn junction is located beneath the buried oxide layer and extends substantially orthogonally with respect to a major surface of the substrate. The device also includes a field plate electrode comprising a semiconductor region located above the buried oxide layer for modifying an electric field at the pn junction by application of a potential to the field plate electrode.

Semiconductor device comprising a PN junction diode

An integrated circuit includes a device including an active region of the device, where the active region of the device includes a channel region having a transverse and a lateral direction. The device further includes an isolation region adjacent to the active region in a traverse direction from the active region, where the isolation region includes a first region located in a transverse direction to the channel region. The isolation region further includes a second region located in a lateral direction from the first region. The first region of the isolation region is under a stress of a first type and the second region of the isolative region is one of under a lesser stress of the first type or of under a stress of a second type being opposite of the first type.

Semiconductor device including an active region and two layers having different stress characteristics

An anti-counterfeiting security circuit is incorporated into an authentic integrated circuit device to induce failure in a counterfeited integrated circuit device by forming the security circuit (e.g.,) with one or more operatively inert high-k metal gate transistors (e.g., HKMG PMOS) having switched or altered work function metal layers () where the security circuit defines a first electrical function with the one or more operatively inert high-k metal gate transistors and defines a second different electrical function if the one or more operatively inert high-k metal gate transistors were instead fabricated as operatively functional high-k metal gate transistors of the first polarity type with a work function metal layer of the first polarity type, the security circuit would define a second different electrical function.

Gate security feature

An electronic device can include a field isolation region and a first insulating layer having a first strain and having a portion, which from a top view, lies entirely within the field isolation region. The electronic device can also include a second insulating layer having a second strain different from the first strain and including an opening. From a top view, the portion of the first insulating layer can lie within the opening in the second insulating layer. In one embodiment, the field isolation region can include a dummy structure and the portion of the first insulating layer can overlie the dummy structure. A process of forming the electronic device can include forming an island portion of an insulating layer wherein from a top view, the island portion lies entirely within the field isolation region.

Process of forming an electronic device including insulating layers having different strains

Electronic device including insulating layers having different strains

A method for forming a via includes forming a gate electrode over a semiconductor substrate, forming a source/drain region in the semiconductor substrate adjacent the gate electrode, forming a silicide region in the source/drain region, forming a post-silicide spacer adjacent the gate electrode after forming the silicide region, forming an interlayer dielectric layer over the gate electrode, the post-silicide spacer, and the silicide region, and forming a conductive via in the interlayer dielectric layer, extending to the silicide region.

Method of forming a via

A method for forming a semiconductor device includes providing a semiconductor substrate; forming a gate dielectric over the semiconductor substrate; forming a gate electrode over the gate dielectric; forming an insulating layer over a sidewall of the gate electrode; defining source and drain regions in the semiconductor substrate adjacent to the insulating layer; implanting a dopant in the source and drain regions of the semiconductor substrate to form doped source and drain regions; forming a sidewall spacer adjacent to the insulating layer; forming a recess in the semiconductor substrate in the source and drain regions, wherein the recess extends directly underneath the spacer a predetermined distance from a channel regions; and forming a stressor material in the recess. The method allows the stressor material to be formed closer to a channel region, thus improving carrier mobility in the channel while not degrading short channel effects.

Method of making a semiconductor device with embedded stressor

An electronic device can include a transistor structure of a first conductivity type, a field isolation region, and a layer of a first stress type overlying the field isolation region. For example, the transistor structure may be a p-channel transistor structure and the first stress type may be tensile, or the transistor structure may be an n-channel transistor structure and the first stress type may be compressive. The transistor structure can include a channel region that lies within an active region. An edge of the active region includes the interface between the channel region and the field isolation region. From a top view, the layer can include an edge the lies near the edge of the active region. The positional relationship between the edges can affect carrier mobility within the channel region of the transistor structure.

Electronic device including a transistor structure having an active region adjacent to a stressor layer

A method for making a semiconductor device is provided which comprises (a) providing a semiconductor structure equipped with a gate () and a channel region, said channel region being associated with the gate; (b) depositing a first sub-layer () of a first stressor material over the semiconductor structure, said first stressor material containing silicon-nitrogen bonds and imparting tensile stress to the semiconductor structure; (c) curing the first stressor material through exposure to a radiation source; (d) depositing a second sub-layer () of a second stressor material over the first sub-layer, said second stressor material containing silicon-nitrogen bonds and imparting tensile stress to the semiconductor structure; and (e) curing the second sub-layer of stressor material through exposure to a radiation source.

Multilayer silicon nitride deposition for a semiconductor device

In a semiconductor fabrication process, an epitaxial layer is formed overlying a substrate, wherein there is a lattice mismatch between the epitaxial layer and the substrate. A hard mask having an opening is formed overlying the epitaxial layer. A recess is formed through the epitaxial layer and into the substrate. The recess is substantially aligned to the opening in the hard mask. A channel region of a semiconductor device is formed in the recess.

Fabrication of a semiconductor device with stressor

A semiconductor device has at least two tensile stressor layers that are cured with UV radiation. A second tensile stressor layer is formed after a first stressor layer. In some examples, the tensile stressor layers include silicon nitride and hydrogen. In some examples, the second tensile stressor layer has a greater shrinkage percentage due to the curing than the first tensile stressor layer. In one form, the second tensile stressor layer after the curing exerts a greater tensile stress than the first tensile stressor layer. The tensile stressors layers are utilized to improve carrier mobility in an N-channel transistor and thus enhance transistor performance. In one form a single group of overlying tensile stressor layers is provided with each layer being increasingly thicker and having increasingly more hydrogen prior to being cured. In other embodiments multiple overlying groups are formed, each group having a similar repeating depth and hydrogen profile.

Method of forming a semiconductor device with multiple tensile stressor layers

A method for making a semiconductor device is provided, comprising (a) providing a semiconductor structure comprising a first gate electrode (); (b) forming a first set of organic spacers () adjacent to said first electrode; (c) depositing a first photo mask () over the structure; and (d) simultaneously removing the first set of organic spacers and the first photo mask.

Disposable organic spacers

A semiconductor fabrication process includes forming isolation structures on either side of a transistor region, forming a gate structure overlying the transistor region, removing source/drain regions to form source/drain recesses, removing portions of the isolation structures to form recessed isolation structures, and filling the source/drain recesses with a source/drain stressor such as an epitaxially formed semiconductor. A lower surface of the source/drain recess is preferably deeper than an upper surface of the recessed isolation structure by approximately 10 to 30 nm. Filling the source/drain recesses may precede or follow forming the recessed isolation structures. An ILD stressor is then deposited over the transistor region such that the ILD stressor is adjacent to sidewalls of the source/drain structure thereby coupling the ILD stressor to the source/drain stressor. The ILD stressor is preferably compressive or tensile silicon nitride and the source/drain structure is preferably silicon germanium or silicon carbon.

Semiconductor process integrating source/drain stressors and interlevel dielectric layer stressors

Growing community of inventors

Austin, TX, United States of America

Paul Grudowski