Infineon Technologies Ag

Infineon Technologies Austria Ag

Paul Ganitzer

Martin Poelzl

Rudolf Zelsacher

Carsten Von Koblinski

Thomas Feil

Markus Zundel

Andreas Peter Meiser

Gerald Lackner

Georg Ehrentraut

Jochen Mueller

Martin Sporn

Tobias Polster

Daniel Kraft

Francisco Javier Santos Rodriguez

Danny Clavette

Franz Hirler

Ralf Otremba

Edward Fuergut

Martin Standing

Oliver Haeberlen

Walter Rieger

Werner Schustereder

Irmgard Escher-Poeppel

Alexander Komposch

Stefan Woehlert

Gerhard Poeppel

Mark Harrison

Kurt Matoy

Erwin Bacher

Hannes Eder

Harald Wiedenhofer

Stephanie Fassl

In an embodiment, a semiconductor package includes a first transistor device having first and second opposing surfaces, a first power electrode and a control electrode arranged on the first surface and a second power electrode arranged on the second surface. A first metallization structure arranged on the first surface includes a plurality of outer contact pads which includes a protective layer of solder, Ag or Sn. A second metallization structure is arranged on the second surface. A conductive connection extending from the first surface to the second surface electrically connects the second power electrode to an outer contact pad of the first metallization structure. A first epoxy layer arranged on side faces and on the first surface of the transistor device includes openings which define a lateral size of the plurality of outer contact pads and a package footprint.

Semiconductor package and methods of manufacturing a semiconductor package

An electronic component includes a semiconductor device including a semiconductor die including a first surface, the first surface including a first metallization structure and edge regions surrounding the first metallization structure, a second surface opposing the first surface and including a second metallization structure, and side faces extending between the first surface and the second surface, wherein the edge regions of the first surface and portions of the side faces are covered by a first polymer layer, wherein the electronic component further includes a plurality of leads and a plastic housing composition, wherein the first metallization structure is coupled to a first lead and the second metallization structure is coupled to a second lead of the plurality of leads.

Composite wafer, semiconductor device and electronic component

A semiconductor device includes a semiconductor layer with a thickness of at most 50 &#x3bc;m. A first metallization structure is disposed on a first surface of the semiconductor layer. The first metallization structure includes a first copper region with a first thickness. A second metallization structure is disposed on a second surface of the semiconductor layer opposite to the first surface. The second metallization structure includes a second copper region with a second thickness.

Semiconductor device with metallization structure on opposite sides of a semiconductor portion

In an embodiment, a composite semiconductor substrate includes a first polymer layer and a plurality of semiconductor dies having a first surface, a second surface opposing the first surface, side faces extending between the first surface and the second surface and a first metallization structure on the first surface. Edge regions of the first surface and at least portions of the side faces are embedded in the first polymer layer. At least one metallic region of the first metallization structure is exposed from the first polymer layer. A second metallization structure is arranged on the second surface of the plurality of semiconductor dies. A second polymer layer is arranged on edge regions of the second surface of the plurality of semiconductor dies and on the first polymer layer in regions between the side faces of neighbouring ones of the plurality of semiconductor dies.

A semiconductor device includes a semiconductor layer with a thickness of at most 50 &#x3bc;m. A first metallization structure is disposed on a first surface of the semiconductor layer. The first metallization structure includes a first copper region with a first thickness. A second metallization structure is disposed on a second surface of the semiconductor layer opposite to the first surface. The second metallization structure includes a second copper region with a second thickness. The total thickness, which is the sum of the first thickness and the second thickness, deviates from the thickness of the semiconductor layer by not more than 20% and a difference between the first thickness and the second thickness is not more than 20% of the total thickness.

In an embodiment, a method includes forming at least one trench in non-device regions of a first surface of a semiconductor wafer, the non-device regions being arranged between component positions, the component positions including device regions and a first metallization structure, applying a first polymer layer to the first surface of a semiconductor wafer such that the trenches and edge regions of the component positions are covered with the first polymer layer and such that at least a portion of the first metallization structure is uncovered by the first polymer layer, removing portions of a second surface of the semiconductor wafer, the second surface opposing the first surface, revealing portions of the first polymer layer in the non-device regions and producing a worked second surface and inserting a separation line through the first polymer layer in the non-device regions to form a plurality of separate semiconductor dies.

Composite wafer, semiconductor device, electronic component and method of manufacturing a semiconductor device

Various embodiments provide a method of reducing a sheet resistance in an electronic device encapsulated at least partially in an encapsulation material, wherein the method comprises: providing an electronic device comprising a multilayer structure and being at least partially encapsulated by an encapsulation material; and locally introducing energy into the multilayer structure for reducing a sheet resistance.

Method of reducing a sheet resistance in an electronic device, and an electronic device

A method of manufacturing a semiconductor device includes forming a separation trench into a first main surface of a semiconductor substrate and removing substrate material from a second main surface of the semiconductor substrate, so as to thin the substrate to a thickness of less than 100 &#x3bc;m, the second main surface being opposite to the first main surface, so as to uncover a bottom side of the trench. Additional methods of manufacturing semiconductor devices are provided.

Methods of manufacturing a semiconductor device by forming a separation trench

A method for manufacturing semiconductor devices is disclosed. In one embodiment a semiconductor substrate having a first surface, a second surface opposite to the first surface and a plurality of semiconductor components is provided. The semiconductor substrate has a device thickness. At least one metallisation layer is formed on the second surface of the semiconductor substrate. The metallisation layer has a thickness which is greater than the device thickness.

Method for manufacturing semiconductor devices having a metallisation layer

In an embodiment of the present invention, a method of forming a semiconductor device includes providing a semiconductor substrate including a first chip region and a second chip region. A first contact pad is formed over the first chip region and a second contact pad is formed over the second chip region. The first and the second contact pads are at least as thick as the semiconductor substrate. The method further includes dicing through the semiconductor substrate between the first and the second contact pads. The dicing is performed from a side of the semiconductor substrate including the first contact pad and the second contact pad. A conductive liner is formed over the first and the second contact pads and sidewalls of the semiconductor substrate exposed by the dicing.

Processing of thick metal pads

A semiconductor workpiece includes a semiconductor substrate, at least two chip areas, components of semiconductor devices being formed in the semiconductor substrate in the at least two chip areas, and a separation trench disposed between adjacent chip areas. The separation trench is formed in a first main surface of the semiconductor substrate and extends from the first main surface to a second main surface of the semiconductor substrate. The second main surface is disposed opposite to the first main surface. The separation trench is filled with at least one sacrificial material.

Semiconductor workpiece having a semiconductor substrate with at least two chip areas

A semiconductor device is manufactured in a semiconductor substrate comprising a first main surface, the semiconductor substrate including chip areas. The method of manufacturing the semiconductor substrate comprises forming components of the semiconductor device in the first main surface in the chip areas, removing substrate material from a second main surface of the semiconductor substrate, the second main surface being opposite to the first main surface, forming a separation trench into a first main surface of the semiconductor substrate, the separation trench being disposed between adjacent chip areas. The method further comprises forming at least one sacrificial material in the separation trench, and removing the at least one sacrificial material from the trench.

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Villach, Austria

Paul Ganitzer