Lsi Logic Corporation

Lsi Corporation

Paul G Filseth

Lav D Ivanovic

Mario Garza

Anatoli Aleksandrovich Bolotov

Mikhail I Grinchuk

Neal Patrick Callan

Kunal N Taravade

Fan Zhang

Shaohua Yang

Zongwang Li

Yang Han

Stanislav V Aleshin

Nicholas K Eib

Ebo H Croffie

George Edward Bailey

Marina M Medvedeva

Eugeni E Egorov

Anton I Sabev

Travis Brist

Gennady V Belokopytov

Mlkhail I Grinchuk

A receive path of a communications system comprises an error-correction decoder, an error-detection decoder, and a codeword adjuster. The error-correction decoder performs error-correction decoding on a received codeword to generate a valid codeword. The error-detection decoder performs error-detection decoding on the valid codeword to determine whether or not the valid codeword is the correct codeword that was transmitted. If the valid codeword is not the correct codeword, then the codeword adjuster generates an adjusted valid codeword by applying an error vector to the valid codeword. The error-detection decoder performs error-detection decoding on the adjusted valid codeword to determine whether or not the adjusted valid codeword is the correct codeword. When the error-correction decoder generates an incorrect valid codeword, adjusting the valid codeword enables the receive path to recover the correct codeword without retransmitting or re-detecting the codeword.

Correcting errors in miscorrected codewords using list decoding

An apparatus having a first circuit and a second circuit is disclosed. The first circuit may be configured to (i) generate second Galois Field elements by performing a first Galois Field inversion on first Galois Field elements, the first Galois Field inversion being different from a second Galois Field inversion defined by an Advanced Encryption Standard and (ii) generate third Galois Field elements by multiplying the second Galois Field elements by an inverse of a predetermined matrix. The second circuit may be configured to (i) generate fourth Galois Field elements by processing the third Galois Field elements in a current encryption round while in a non-skip mode, (ii) generate fifth Galois Field elements by multiplying the fourth Galois Field elements by the predetermined matrix and (iii) present the fifth Galois Field elements as updated versions of the first Galois Field elements in advance of a next encryption round.

Alternate galois field advanced encryption standard round

The present invention is a cryptoengine configured for providing countermeasures against attacks, including: an input/output (I/O) control unit, a memory, a controller, and an Arithmetic Logic Unit (ALU). The memory is communicatively coupled with the I/O control unit, receives inputs from the I/O control unit, and provides outputs to the I/O control unit based upon the received inputs. The controller is communicatively coupled with the I/O control unit for transmitting and receiving control signals. The ALU includes a plurality of storage components and computational components. The ALU is communicatively coupled with the controller and receives commands from/transmits status bits and flags to the controller. The ALU is further communicatively coupled with the memory and is configured for providing output signals to/receiving input signals from the memory. Further, the cryptoengine is configured for being communicatively coupled with a host computing device.

High performance arithmetic logic unit (ALU) for cryptographic applications with built-in countermeasures against side channel attacks

An architecture for a block cipher, where the architecture includes functional units that are logically reconfigurable so as to be able to both encrypt clear text into cipher text and decrypt cipher text into clear text using more than one block cipher mode based on at least one of advanced encryption standard and data encryption standard.

Multimode block cipher architectures

The present invention is directed to a method and system of intelligent dummy filling placement to reduce inter-layer capacitance caused by overlaps of dummy filling area on successive layers. The method and system treats each consecutive pair of layers together so as to minimize dummy filling overlaps between each layer. In particular, dummy fill features on each layer may be placed in a checkerboard pattern to avoid overlaps. As such, the present invention may eliminate large overlap area of the dummy patterns on consecutive layers by utilizing intelligent dummy filling placement.

Method and system for reducing inter-layer capacitance in integrated circuits

A circuit for implementing elliptic curve and hyperelliptic curve encryption and decryption operations, having a read only memory with no more than about two kilobytes of accessible memory, containing first programming instructions. An arithmetic logic unit has access to second programming instructions that are resident in a gate-level program disposed in the arithmetic logic unit, and is operable to receive data from no more than one input FIFO register. A microcontroller has no more than about two thousand gates, and is adapted to read the first programming instructions from the read only memory, send control signals to the arithmetic logic unit, and receive flags from the arithmetic logic unit. The arithmetic unit reads the third programming instructions, selectively performs elliptic curve and hyperelliptic curve encryption and decryption operations on the data according to the second programming instructions and the microcontroller, and sends output to no more than one output FIFO register.

Flexible hardware architecture for ECC/HECC based cryptography

A method and system of optimizing the illumination of a mask in a photolithography process. A specific, preferred method includes the steps of: loading minimum design rules of a layout, loading exposure latitude constraints, loading mask error constraints, loading initial illumination conditions, simulating current illumination conditions, obtaining dose-to-print threshold from the minimum design rules (i.e., lines-and-space feature), applying OPC on the layout using the dose-to-print threshold, calculating DOF using the exposure latitude and mask error constraints, changing the illumination conditions in order to attempt to maximize common DOF with the exposure latitude and mask error constraints, and continuing the process until maximum common DOF is obtained.

OPC based illumination optimization with mask error constraints

A computer-implemented method is disclosed for recognizing edges in a digital image having a plurality of pixels with gray-scale values defining features. The method includes recognizing edges of the features by cearting a new image in which pixels in the new image corresponding to pixels in the gray-scale image that have a brightness value meeting a predetermined threshold are assigned a first binary value to represent edge regions, while remaining pixels in the new image are assigned a second value to represent both background and internal areas of the features. Area recognition is then performed to distinguish internal feature areas from background areas. The method further includes detecting edge lines from the edge regions that separate features from background and internal feature areas.

Adaptive Sem edge recognition algorithm

A method and system for detecting defects in a physical mask used for fabricating a semiconductor device having multiple layers is disclosed, where each layer has a corresponding mask. The method and system include receiving a digital image of the mask, and automatically detecting edges of the mask in the image using pattern recognition. The detected edges, which are stored in a standard format, are imported along with processing parameters into a process simulator that generates an estimated aerial image of the silicon layout that would be produced by a scanner using the mask and the parameters. The estimated aerial image is then compared to an intended aerial image of the same layer, and any differences found that are greater than predefined tolerances are determined to horizontal defects. In addition, effects that the horizontal defects may have on adjacent layers are analyzed to discover vertical defects.

Mask defect analysis for both horizontal and vertical processing effects

Local images of photolithographic masks are assigned to classes based on similarity of functions of circuits formed by the images, so that all of the images of a class can be corrected by correcting one of the members. Boundaries of photolithographic masks are corrected for diffusion of light by moving regions based on process light intensity and proximity of close connections. Boundaries are also corrected for shifting of photoactive material in photoresists by calculating the amount of shift based on light intensities at pattern points.

Mask correction for photolithographic processes

A method and system is provided for automatically calibrating a masking process simulator using a calibration mask and process parameters to produce a calibration pattern on a wafer. A digital image is created of the calibration pattern, and the edges of the pattern are detected. Data defining the calibration mask and at least one of the process parameters are input to a process simulator to produce an alim image estimating the calibration pattern that would be produced by the masking process. The alim image and the detected edges of the digital image are then overlaid, and a distance between contours of the pattern in the alim image and the detected edges is measured. One or more mathematical algorithms are used to iteratively change the values of the processing parameters until a set of processing parameter values are found that produces a minimum distance between the contours of the pattern in the alim image and the detected edges.

Automatic calibration of a masking process simulator

An improved process simulation system for simulating results of fabrication process for a semiconductor device design is disclosed. According to the method and system disclosed herein, the process simulator receives processing parameters and mask data for at least two masks as input, and simulates results of the fabrication process such that an aerial image is generated for each layer of the device that was simulated. After generating the aerial images, the process simulator superimposes the aerial images to create a composite image. An operator is then allowed to misalign at least one of the images in relation to the other images based on one or more offset values. The composite image showing the misalignment is then displayed, allowing the operator to view nominal process capability as well as process fluctuations prior to fabrication of the semiconductor device.

Wafer process critical dimension, alignment, and registration analysis simulation tool

A method and system for automatically calibrating a masking process simulator using a calibration mask and process parameters to produce a calibration pattern on a wafer. A digital image is created of the calibration pattern, and the edges of the pattern are detected. Data defining the calibration mask and the process parameters are input to a process simulator to produce an alim image estimating the calibration pattern that would be produced by the masking process. The alim image and the detected edges of the digital image are then overlaid, and a distance between contours of the pattern in the alim image and the detected edges is measured. One or more mathematical algorithms are used to iteratively change the values of the processing parameters until a set of processing parameter values are found that produces a minimum distance between the contours of the pattern in the alim image and the detected edges.

A method for adjusting preliminary feature position characteristics of a preliminary mask pattern on a mask to produce a desired etch pattern on a substrate having desired feature position characteristics.

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Los Gatos, CA, United States of America

Paul G Filseth