Rambus Inc.

Other

Intel Corporation

Microchip Technology Inc.

Tabula, Inc.

Paul G Davis

Craig Edward Hampel

Richard Maurice Barth

Frederick Abbott Ware

Ely K Tsern

Donald C Stark

Abhijit Mukun Abhyankar

David Nguyen

James A Gasbarro

Bradley A May

Todd W Bystrom

Kevin S Donnelly

Stefanos Sidiropoulos

Bruno Werner Garlepp

Pak Shing Chau

Clemenz L Portmann

Andrew V Anderson

Thomas J Holman

Jared L Zerbe

William Franklin Stonecypher

Michael Tak-Kei Ching

Andy Peng-Pui Chan

Peter D MacWilliams

John Bradly Dillon

Pradeep Batra

Ramprasad Satagopan

John C Peck, Jr

Karnamadakala Krishnamohan

Quoc B Huynh

James A Gasborro

James A Gasbarre

Methods of operation of a memory device and system are provided in embodiments. Initialization operations are conducted at a first frequency of operation during an initialization sequence. Memory access operations are then performed at a second frequency of operation. The second frequency of operation is higher than the first frequency of operation. Also, the memory access operations include a read operation and a write operation. In an embodiment, information that represents the first frequency of operation and the second frequency of operation is read from a serial presence detect device.

Controlling DRAM at time DRAM ready to receive command when exiting power down

For an integrated circuit (IC) that retrieves data from a memory device external to the IC, a novel memory interface module that generates a sampling clock to the memory device and samples the retrieved data is described. The memory interface module adjusts the frequency of the sampling clock and selects a sampling time for sampling the retrieved data. The memory interface includes a training module that monitors a data pin of the memory device for transitions. The training module searches and records the earliest transition and the latest transition with respect to the period of the sampling clock. The memory interface module uses the earliest transition and the latest transition to determine an interval of data uncertainty (uncertainty interval) for the data pin. The memory interface module facilitates determining a new sampling time and a new sampling clock frequency based on the uncertainty intervals.

Serial peripheral interface

An apparatus for controlling a dynamic random access memory (DRAM), the apparatus comprising an interface to transmit, over a first plurality of wires, to the DRAM a first code to indicate that first data is to be written to the DRAM and a column address to indicate a column location of a memory core in the DRAM where the first data is to be written. The interface is further to transmit a second code to indicate whether mask information for the first data will be sent to the DRAM. If the second code indicates that mask information will be sent, a portion of the column address and a portion of the mask information are sent after the second code is sent. The interface is further to transmit to the DRAM, over a second plurality of wires separate from the first plurality of wires, the first data.

Method and apparatus for indicating mask information

A method for storing data in a memory chip that includes a memory core having dynamic random access memory cells, is performed by a memory controller chip. The method includes sending a write command to a first interface of the memory chip, wherein the write command specifies a write operation. After sending the write command, the memory controller chip waits for a first time period corresponding to a time period during which the write command is stored by the memory chip, and sends data associated with the write operation to a second interface of the memory chip, wherein the sending of the data occurs after a second time period transpires, the second time period following the first time period, such that sending the write command and sending the data are separated by a first predetermined delay time that includes both the first time period and the second time period.

Memory component having write operation with multiple time periods

A method and apparatus for adjusting the performance of a memory system is provided. A memory system comprises a master device and a slave device. A memory channel couples the master device to the slave device such that the slave device receives the system operating information from the master device via the memory channel. The slave device further includes tuning circuitry within the slave device such that the performance of the memory system is improved.

Method and apparatus for adjusting the performance of a synchronous memory system

A memory controller has an interface to convey, over a first set of interconnect resources: a first command that specifies activation of a row of memory cells, a second command that specifies a write operation directed to the row of memory cells, a bit that specifies whether precharging will occur in connection with the write operation, a code that specifies whether data mask information will be issued in connection with the write operation, and if the code specifies that data mask information will be issued, data mask information that specifies whether to selectively write portions of write data associated with the write operation. The memory controller interface further conveys, over a second set of interconnect resources, separate from the first set of interconnect resource, the write data.

Memory controller for controlling write signaling

A memory component includes a memory core, a control transport block to receive a write command from external control lines, and a write control buffer to store the write command for a first time period after the write command is received at the transport block. A data buffer receives data from external data lines, the data to be stored in the memory core in response to the write command, wherein receipt of the data occurs based on a second time period that follows the first time period, such that receipt of the write command and the data are separated by a delay time that includes both the first time period and the second time period. A write mask buffer receives write masking information from an external write mask line. Receipt of the write command and the write masking information are separated by the delay time.

Method of operation of a memory device and system including initialization at a first frequency and operation at a second frequency and a power down exit mode

In a method of controlling a memory device, the following is conveyed over a first set of interconnect resources: a first command that specifies activation of a row of memory cells; a second command that specifies a write operation, wherein write data is written to the row; a bit that specifies whether precharging occurs after the write data is written; and a code that specifies whether data mask information will be issued for the write operation. If the code specifies that the information will be issued, then the information, which specifies whether to selectively write portions of the write data, is conveyed over the first set of interconnect resources after conveying the code. The write data to be written in connection with the write operation is conveyed over a second set of interconnect resources that is separate from the first set of interconnect resources.

Memory write signaling and methods thereof

A method of operating a memory component that includes a memory core includes receiving, from external control lines, a write command that specifies a write operation. The write command is stored for a first time period after receiving the write command. After the first time period, the write operation is initiated in response to the write command. During the write operation, unmasked portions of received data are written to the memory core, where the unmasked portions of the data are bits of the data that are identified by received mask information as not being masked.

Memory system and method for two step memory write operations

A method for providing field updates through the use of a memory emulation circuit with a content addressable memory (CAM) as the intelligent portion of the emulation circuit's arbiter. CAM circuitis comprised of configurable memory and is initially unprogrammed. Address requests are passed straight through multiplexerto Read Only Memory (ROM). As a result the data in the data location in ROMthat corresponds to the requested address will be output to data bus. If data locations in ROMbecome defective or contain data that needs to be upgraded the circuit implements a remapping of the data location. CAM circuitis programmed with direct addresses to be replaced in ROM. The direct addresses are paired to emulation addresses of data locations in configurable memory. Upgraded or substitute data is programmed into the configurable memoryat the paired emulation address. When address requests are received thereafter, CAM circuitcompares the address request to its stored direct addresses. If a match is found the paired emulation address is passed through multiplexerinstead of the direct address. As a result, the substitute or upgraded data in configurable memoryis output to data busin place of the old data.

Method and apparatus for updating data in ROM using a CAM

A semiconductor memory device includes a memory core, a first interface to receive write data from a first set of interconnect resources, and a second interface, separate from the first interface, to receive from a second set of interconnect resources a column address and a first code. The column address is associated with the write data and identifies a column of the memory core in which to store the write data. The first code indicates whether the write data is selectively masked by data mask information. If the first code indicates that the write data is selectively masked, the second interface is to receive data mask information specifying whether to selectively write portions of the write data to the memory core.

Interface for a semiconductor memory device and method for controlling the interface

A system comprising a storage location to store information representing a timing parameter pertaining to a random access memory device. An integrated circuit device generates a value that is representative of a period of time that elapses between the random access memory device exiting from a power down mode and a time at which the random access memory device is capable of receiving a command. The integrated circuit device generates the value from the information representing the timing parameter pertaining to the random access memory device.

System for a memory device having a power down mode and method

A memory device including an array of memory cells, and a register circuit to store a value representative of a period of time to elapse before the memory device is ready to receive a command when recovering from a power down mode is provided in an embodiment. The command specifies an access to the array of memory cells. A delay lock loop circuit synchronizes data transfers using an external clock signal. The delay lock loop circuit reacquires synchronization with the external clock signal during the period of time.

Memory device having a power down exit register

A memory module comprises a memory device including a memory array to store data. An interface receives an instruction to exit a power down mode. A register stores a value representative of a period of time to elapse between exiting from the power down mode and a time at which the memory device is capable of receiving a command to access the data. A storage device stores a plurality of parameter information that pertains to the memory device. The value is based on at least a first parameter information of the plurality of parameter information.

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San Jose, CA, United States of America

Paul G Davis