International Business Machines Corporation

Infineon Technologies Ag

Paul David Agnello

Cyril Cabral, Jr

Jed Hickory Rankin

Arne Watson Ballantine

James William Adkisson

Ronnen Andrew Roy

Erin C Jones

Devendra K Sadana

Yun Yu Wang

Rama Divakaruni

Edward J Nowak

Christian Lavoie

Thomas O Sedgwick

Lawrence Alfred Clevenger

Anthony K Stamper

Stephen W Bedell

Keith E Fogel

Ramachandra Divakaruni

Alfred Grill

Kirk David Peterson

Christopher Vincent Jahnes

Robert H Dennard

Anthony Gene Domenicucci

Roy Arthur Carruthers

John Patrick Hummel

Robert J Purtell

Leena Paivikki Buchwalter

James McKell Edwin Harper

Thomas John Licata

Barbara Jean Luther

Jean Louise Jordan-Sweet

Ghavam G Shahidi

Judson Robert Holt

Dominic Joseph Schepis

Subramanian Srikanteswara Iyer

Shreesh Narasimha

Bomy A Chen

Matthew Warren Copel

Byeong Yeol Kim

K Paul Muller

Terence Lawrence Kane

Paul Stephen McLaughlin

Rajeev Malik

Dennis Sinitsky

Xiaomeng Chen

Scott W Crowder

Mukesh Vijay Khare

Heemyong Park

Byoung Hun Lee

Peter I Smeys

Francois M d'Heurle

Tung-Sheng Kuan

Dirk Karl Manger

Keith Kwong Hon Wong

Christopher Stephen Putnam

Qi-Zhong Hong

Nivo Rovedo

Sunfei Fang

Patrick William Dehaven

Chester T Dziobkowski

Richard J Murphy

Hsiang-Jen Huang

Detlev A Gruetzmacher

Qi-Zong Hong

Thermal mixing methods of forming a substantially relaxed and low-defect SGOI substrate material are provided. The methods include a patterning step which is used to form a structure containing at least SiGe islands formed atop a Ge resistant diffusion barrier layer. Patterning of the SiGe layer into islands changes the local forces acting at each of the island edges in such a way so that the relaxation force is greater than the forces that oppose relaxation. The absence of restoring forces at the edges of the patterned layers allows the final SiGe film to relax further than it would if the film was continuous.

Relaxed low-defect SGOI for strained SI CMOS applications

A semiconductor structure includes an epitaxial surface semiconductor layer having a first dopant polarity and a first crystallographic orientation, and a laterally adjacent semiconductor-on-insulator surface semiconductor layer having a different second dopant polarity and different second crystallographic orientation. The epitaxial surface semiconductor layer has a first edge that has a defect and an adjoining second edge absent a defect. Located within the epitaxial surface semiconductor layer is a first device having a first gate perpendicular to the first edge and a second device having a second gate perpendicular to the second edge. The first device may include a performance sensitive logic device and the second device may include a yield sensitive memory device. An additional semiconductor structure includes a further laterally adjacent second semiconductor-on-insulator surface semiconductor layer having the first polarity and the second crystallographic orientation, and absent edge defects, to accommodate yield sensitive devices.

Multiple crystallographic orientation semiconductor structures

Methods for preventing cavitation in high aspect ratio dielectric regions in a semiconductor device, and the device so formed, are disclosed. The invention includes depositing a first dielectric in the high aspect ratio dielectric region between a pair of structures, and then removing the first dielectric to form a bearing surface adjacent each structure. The bearing surface prevents cavitation of the interlayer dielectric that subsequently fills the high aspect ratio region.

Preventing cavitation in high aspect ratio dielectric regions of semiconductor device

A double gated silicon-on-insulator (SOI) MOSFET is fabricated by forming epitaxially grown channels, followed by a damascene gate. The double gated MOSFET features narrow channels, which increases current drive per layout width and provides low out conductance.

Method of fabricating semiconductor side wall fin

Relaxed, low-defect SGOI for strained Si CMOS applications

A field effect transistor is formed with a sub-lithographic conduction channel and a dual gate which is formed by a simple process by starting with a silicon-on-insulator wafer, allowing most etching processes to use the buried oxide as an etch stop. Low resistivity of the gate, source and drain is achieved by silicide sidewalls or liners while low gate to junction capacitance is achieved by recessing the silicide and polysilicon dual gate structure from the source and drain region edges.

Double gate trench transistor

A method of producing electrical contacts having reduced interface roughness as well as the electrical contacts themselves are disclosed herein. The method of the present invention comprises (a) forming an alloy layer having the formula MX, wherein M is a metal selected from the group consisting of Co and Ni and X is an alloying additive, over a silicon-containing substrate; (b) optionally forming an optional oxygen barrier layer over said alloy layer; (c) annealing said alloy layer at a temperature sufficient to form a MXSi layer in said structure; (d) removing said optional oxygen barrier layer and any remaining alloy layer; and optionally (e) annealing said MXSi layer at a temperature sufficient to form a MXSilayer in said structure.

Structure for controlling the interface roughness of cobalt disilicide

A method of forming a salicide on a semiconductor device includes depositing a first refractory metal layer over a silicon region of a substrate, depositing a near-noble metal layer over the first refractory metal layer, and depositing a second refractory metal layer over the near-noble metal layer. The semiconductor device is annealed in a first annealing process to form a silicide layer abutting the doped region of the semiconductor device. Un-reacted portions of the near-noble metal layer and the second refractory metal layer are removed. The device may be annealed in an optional second annealing process to convert the silicide layer to a low resistance phase silicide material. Junction leakage and bridging are minimized or eliminated by embodiments of the present invention, and a smoother silicided surface is achieved.

Salicide formation method

A method and structure for a CMOS device comprises depositing a silicon over insulator (SOI) wafer over a buried oxide (BOX) substrate, wherein the SOI wafer has a predetermined thickness; forming a gate dielectric over the SOI wafer, forming a shallow trench isolation (STI) region over the BOX substrate, wherein the STI region is configured to have a generally rounded corner; forming a gate structure over the gate dielectric; depositing an implant layer over the SOI wafer; performing one of N-type and P-type dopant implantations in the SOI wafer and the implant layer; and hearing the device to form source and drain regions from the implant layer and the SOI wafer, wherein the source and drain regions have a thickness greater than the predetermined thickness of the SOI wafer, wherein the gate dielectric is positioned lower than the STI region.

CMOS device on ultrathin SOI with a deposited raised source/drain, and a method of manufacture

A method and structure for a CMOS device comprises depositing a silicon over insulator (SOI) wafer over a buried oxide (BOX) substrate, wherein the SOI wafer has a predetermined thickness; forming a gate dielectric over the SOI wafer; forming a shallow trench isolation (STI) region over the BOX substrate, wherein the STI region is configured to have a generally rounded corner; forming a gate structure over the gate dielectric; depositing an implant layer over the SOI wafer; performing one of N-type and P-type dopant implantations in the SOI wafer and the implant layer; and heating the device to form source and drain regions from the implant layer and the SOI wafer, wherein the source and drain regions have a thickness greater than the predetermined thickness of the SOI wafer, wherein the gate dielectric is positioned lower than the STI region.

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Wappingers Falls, NY, United States of America

Paul David Agnello