Cypress Semiconductor Corporation

Paul D Berndt

Steven Philip Larky

Scott Allen Swindle

Jarie G Bolander

Leah S Clark

Warren A Snyder

Mike Lewis

In one embodiment, an integrated circuit includes a serial link interface configured to send and receive data over a serial bus both during normal operation and during scan tests. The integrated circuit may include data routing circuitry for transferring data between the serial link interface and a scan chain during a scan test, and for transferring data between the serial link interface and a core logic circuit of the integrated circuit, without going through the scan chain, during normal operation. Scan data may be generated and analyzed by a tester integrated circuit coupled to the integrated circuit over the serial bus.

Scan testing of integrated circuits with high-speed serial interface

An apparatus coupled to a low speed tester and a device is disclosed. The device may have a first speed faster than a second speed of the low speed tester. The apparatus may be configured to allow the low speed tester to perform high speed tests of the device at the first speed.

Apparatus and method to test high speed devices with a low speed tester

In one embodiment, a test circuit is coupled to receive a first signal from a signal generator such as a test equipment. The test circuit allows access to one or more terminals of a first integrated circuit, a second integrated circuit, or both based at least on the signal. The test circuit may be in the first integrated circuit. The first integrated circuit and the second integrated circuit may be in a single package. In one embodiment, the test circuit routes signals to and from the second integrated circuit, thus allowing the second integrated circuit to be tested as if it was stand-alone. In one embodiment, the test circuit allows access to otherwise inaccessible terminals of the first integrated circuit, the second integrated circuit, or both.

System and method for testing multiple integrated circuits that are in the same package

A circuit comprising a memory array having a first region, a second region, a plurality of bitlines and an X-decoder. A plurality of transistors may each coupled between the first and second regions, where each of the transistors may be configured to (i) separate the first and the second region during a read operation and (ii) join the first and the second region during a write operation. Alternatively, a plurality of memory regions may be implemented, each separated by another plurality of transistors.

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Woodinville, WA, United States of America

Paul D Berndt