International Business Machines Corporation

Tokyo Electron Limited

Other

Canon Anelva Corporation

Paul Charles Jamison

Hemanth Jagannathan

Vijay Narayanan

Takashi Ando

Choonghyun Lee

Ruqiang Bao

Eduard Albert Cartier

Vamsi Krishna Paruchuri

Sufi Zafar

Evgeni Petrovich Gousev

Alessandro Cesare Callegari

Christopher Peter D'Emic

Michael Abramovich Gribelyuk

Lisa F Edge

Rajarao Jammy

Fenton Read McFeely

Dianne L Lacey

Cyril Cabral, Jr

John Rozen

Cory Wajda

Supratik Guha

Martin Michael Frank

Deborah A Neumayer

Barry P Linder

John Greg Massey

Steven Consiglio

Kangguo Cheng

Alexander Reznicek

Ali Khakifirooz

Brent A Anderson

Kevin K Chan

Richard Stephan Wise

Thomas N Adam

John Anthony Fitzsimmons

Koji Watanabe

Kandabara N Tapily

Alessandro Curioni

Gert J Leusink

Nestor Alexander Bojarczuk, Jr

Pushkar Ranade

Changhwan Choi

Mukesh Vijay Khare

James J Quinlivan

Thomas H Ivers

Beth A Ward

Marinus J P Hopstaken

Lars-Ake Ragnarsson

Wanda Andreoni

Thomas T Hwang

Takaaki Tsunomura

Carlo A Pignedoli

Juntao Li

Daniel C Edelstein

Sampath Purushothaman

Soon-Cheon Seo

Timothy Joseph Dalton

Stephen McConnell Gates

Sanjay C Mehta

Kisik Choi

Hiroyuki Miyazoe

Robert Daniel Clark

Yun-Yu Wang

Richard Anthony Conti

Matthew Warren Copel

Kwong Hon Wong

Nicole A Saulnier

Yumiko Kawano

David Edward Kotecki

Dexin Kong

Ying Li

Hideaki Yamasaki

David L O'Meara

Scott David Halle

Kang-Wook Lee

Joseph Francis Shepard, Jr

Hongwen Yan

Ashima B Chakravarti

Darryl D Restaino

Stephan Alan Cohen

Lynne Marie Gignac

Youngseok Kim

An L Steegen

Nestor A Bojarczuk, Jr

Douglas Andrew Buchanan

Tuan Anh Vo

Horatio Seymour Wildman

Marinus Hopstaken

Tsuyoshi Takahashi

Iqbal Rashid Saraf

Glen L Miles

Victor Ku

Ernest N Levine

Donna Rizzone Cote

Tina Jane Wagner

Chester T Dziobkowski

Eva Erika Simonyi

Kristen Scheer

Kazuhito Nakamura

Frank V Liucci

Frank Grellner

Structures and methods are provided for integrating a resistance random access memory (ReRAM) in a back-end-on-the-line (BEOL) fat wire level. In one embodiment, a ReRAM device area contact structure is provided in the BEOL fat wire level that has at least a lower via portion that contacts a surface of a top electrode of a ReRAM device area ReRAM-containing stack. In other embodiments, a tall ReRAM device area bottom electrode is provided in the BEOL fat wire level and embedded in a dielectric material stack that includes a dielectric capping layer and an interlayer dielectric material layer.

BEOL fat wire level ground rule compatible embedded artificial intelligence integration

A method of controlling the forming voltage of a dielectric film in a resistive random access memory (ReRAM) device. The method includes depositing a dielectric film contains intrinsic defects on a substrate, forming a plasma-excited treatment gas containing Hgas, and exposing the dielectric film to the plasma-excited treatment gas to create additional defects in the dielectric film without substantially changing a physical thickness of the dielectric film, where the additional defects lower the forming voltage needed for generating an electrically conducting filament across the dielectric film. The dielectric film can include a metal oxide film and the plasma-excited treatment gas may be formed using a microwave plasma source.

Method for controlling the forming voltage in resistive random access memory devices

Embodiments of the present invention are directed to a back-end-of-line (BEOL) compatible metal-insulator-metal on-chip decoupling capacitor (MIMCAP). This BEOL compatible process includes a thermal treatment for inducing an amorphous-to-cubic phase change in the insulating layer of the MIM stack prior to forming the top electrode. In a non-limiting embodiment of the invention, a bottom electrode layer is formed, and an insulator layer is formed on a surface of the bottom electrode layer. The insulator layer can include an amorphous dielectric material. The insulator layer is thermally treated such that the amorphous dielectric material undergoes a cubic phase transition, thereby forming a cubic phase dielectric material. A top electrode layer is formed on a surface of the cubic phase dielectric material of the insulator layer.

Back-end-of-line compatible metal-insulator-metal on-chip decoupling capacitor

A semiconductor structure, and a method of making the same includes a multiple electrode stacked capacitor containing a sequence of first metal layers interleaved with second metal layers. A quad-layer stack separates each of the first metal layers from each of the second metal layers, the quad-layer dielectric stack includes a first dielectric layer made of AlO, a second dielectric layer made of HfO, a third dielectric layer made of AlO, and a fourth dielectric layer made of HfO.

Quad-layer high-k for metal-insulator-metal capacitors

A method of forming a vertical fin field effect transistor device, including, forming one or more vertical fins with a hardmask cap on each vertical fin on a substrate, forming a fin liner on the one or more vertical fins and hardmask caps, forming a sacrificial liner on the fin liner, and forming a bottom spacer layer on the sacrificial liner.

Approach to control over-etching of bottom spacers in vertical fin field effect transistor devices

A method for forming a metal-insulator-metal (MIM) capacitor on a semiconductor substrate is presented. The method includes forming a first electrode defining columnar grains, forming a dielectric layer over the first electrode, and forming a second electrode over the dielectric layer. The first and second electrodes can be titanium nitride (TiN) electrodes. The dielectric layer can include one of hafnium oxide and zirconium oxide deposited by atomic layer deposition (ALD). The ALD results in deposition of high-k films in grain boundaries of the first electrode.

Surface area enhancement for stacked metal-insulator-metal (MIM) capacitor

According to an embodiment of the present invention, a semiconductor structure includes a semiconductor substrate and a plurality of fins located on the semiconductor substrate. The plurality of fins each independently includes a bottom fin portion, a top fin portion layer, and an isolated oxide layer located in between the bottom fin portion and the top fin portion layer in the y-direction parallel to the height of the plurality of fins. The isolated oxide layer includes a mixed oxide region located in between oxidized regions in an x-direction perpendicular to the height of the plurality of fins.

Oxide isolated fin-type field-effect transistors

An electrical device that includes a p-type semiconductor device having a p-type work function gate structure including a first high-k gate dielectric, a first metal containing buffer layer, a first titanium nitride layer having a first thickness present on the metal containing buffer layer, and a first gate conductor contact. A mid gap semiconductor device having a mid gap gate structure including a second high-k gate dielectric, a second metal containing buffer layer, a second titanium nitride layer having a second thickness that is less than the first thickness present, and a second gate conductor contact. An n-type semiconductor device having an n-type work function gate structure including a third high-k gate dielectric present on a channel region of the n-type semiconductor device, a third metal containing buffer layer on the third high-k gate dielectric and a third gate conductor fill present atop the third metal containing buffer layer.

Complementary metal oxide semiconductor replacement gate high-k metal gate devices with work function adjustments

A technique relates to a semiconductor device. A gate stack is formed on a fin, the gate stack being formed to have a length in a vertical direction. A gate contact is formed adjacent to the gate stack for the length of the gate stack in the vertical direction.

Gate first technique in vertical transport FET using doped silicon gates with silicide

A tri-layer dielectric stack is provided for a metal-insulator-metal capacitor (MIMCAP). Also, a metal-insulator-metal capacitor (MIMCAP) is provided having three or more electrodes. The tri-layer dielectric stack includes a first layer formed from a first metal oxide electrical insulator. The tri-layer dielectric stack further includes a second layer, disposed over the first layer, formed from ZrO. The tri-layer dielectric stack also includes a third layer, disposed over the second layer, formed from a second metal oxide electrical insulator.

Multilayer dielectric for metal-insulator-metal capacitor (MIMCAP) capacitance and leakage improvement

Capacitors and methods of forming the same include forming a dielectric layer on a first metal layer. The dielectric layer is oxygenated such that interstitial oxygen is implanted in the dielectric layer. A second metal layer is formed on the dielectric layer. The dielectric layer is heated to release the interstitial oxygen and to oxidize the first and second metal layers at interfaces between the dielectric layer and the first and second metal layers.

Leakage current reduction in stacked metal-insulator-metal capacitors

Growing community of inventors

Hopewell Junction, NY, United States of America

Paul Charles Jamison