International Business Machines Corporation

Other

Globalfoundries Inc.

Stmicroelectronics Gmbh

Renesas Electronics America Inc.

Paul Andrew Ronsheim

Jack Oon Chu

Omer H Dokumaci

Tze-Chiang Chen

Rajarao Jammy

Johnathan E Faltermeier

Ulrike Gruening

Huajie Chen

Paul Christian Parries

Hiroyuki Akatsu

Christopher Carr Parks

Anda C Mocuta

Rajesh Rengarajan

Yujun Li

Dan Mihai Mocuta

Suryanarayan G Hegde

Martin Revitz

Susan E Chaloux

Effendi Leobandung

Jack Allan Mandelman

Ghavam G Shahidi

Nicolas J Loubet

Kevin K Chan

Michael S Gordon

Judson Robert Holt

Cyril Cabral, Jr

Michael Patrick Chudzik

Sanjay C Mehta

Renee Tong Mo

Pranita Kulkarni

Jinping Liu

Yun-Yu Wang

Henry K Utomo

Michael John Hargrove

Shahab Siddiqui

Werner A Rausch

Joseph Francis Shepard, Jr

Anthony Gene Domenicucci

Seshadri Subbanna

Chang-Ming Hsieh

Kam-Leung Lee

Michael Abramovich Gribelyuk

Min Dai

Manu J Tejwani

Scott W Crowder

Kingsuk Maitra

David C Ahlgren

Ronald W Knepper

Woo-Hyeong Lee

Mary Joseph Saccamango

Mukesh Vijay Khare

Dmitriy Shneyder

Richard J Murphy

Zhengmao Zhu

Heemyong Park

Victor R Nastasi

Russell C Lange

Robert K Cook

Nathaniel C Berliner

Liang-Kai Han

Bob H Yun

Jean-Marc Rousseau

David M Rockwell

Ryan Matthew Mitchell

Michael Hatzistergos

Thomas T Hwang

Jonathan Levy

Subodh K Kulkarni

David A Sunderland

Liesl M McMurray, Legal Representative

Cristina Plettner

Toyoji Yamamoto

Christopher Michael Molella

Vincent Vazquez

Jeff McMurray

A method of forming a semiconductor device is disclosed. The method includes: forming a dielectric region on a substrate; annealing the dielectric region in an environment including ammonia (NH); monitoring a nitrogen peak of at least one of the substrate and the dielectric region during the annealing; and adjusting a parameter of the environment based on the monitoring of the nitrogen peak.

Method of manufacturing scaled equivalent oxide thickness gate stacks in semiconductor devices and related design structure

A method of making a semiconductor device patterns a first fin in a pFET region, and patterns a second fin in an nFET region. A plurality of conformal microlayers containing a straining material are deposited on the first and second fins. A protective cap material is formed on the first fin, and the conformal layers are selectively removed from the second fin. The straining material is then thermally diffused into the first fin. The protective cap material is removed from the first fin after the thermal annealing and after the conformal micro layers are selectively removed from the second fin.

Method to enable compressively strained pFET channel in a FinFET structure by implant and thermal diffusion

A specimen handling apparatus is provided and includes a body in which a bore is defined and a needle having a tip portion and a bit, which is removably insertible into the bore with the tip portion at least partially exposed, the bore and the bit each being formed such that, when the bit is inserted into the bore, the needle is forced into one of first or second rotational positions relative to a long axis thereof.

Specimen handling apparatus

A structure and a method for operating the same. The method includes providing a detecting structure which includes N detectors. N is a positive integer. A fabrication step is simultaneously performed on the detecting structure and M product structures in a fabrication tool resulting in a particle-emitting layer on the detecting structure. The detecting structure is different than the M product structures. The M product structures are identical. M is a positive integer. An impact of emitting particles from the particle-emitting layer on the detecting structure is analyzed after said performing is performed.

Particle emission analysis for semiconductor fabrication steps

A method of forming a semiconductor device is provided that includes forming a gate structure atop a substrate and implanting dopants into the substrate to a depth of 10 nm or less from an upper surface of the substrate. In a following step, an anneal is performed with a peak temperature ranging from 1200&#xb0; C. to 1400&#xb0; C., and a hold time period ranging from 1 millisecond to 5 milliseconds.

Shallow extension regions having abrupt extension junctions

The present invention provides a method for retarding the diffusion of dopants from a first material layer (typically a semiconductor) into an overlayer or vice versa. In the method of the present invention, diffusion of dopants from the first semiconductor into the overlayer or vice versa is retarded by forming a monolayer comprising carbon and oxygen between the two layers. The monolayer is formed in the present invention utilizing a chemical pretreatment process in which a solution including iodine and an alcohol such as methanol is employed.

Chemical treatment to retard diffusion in a semiconductor overlayer

A method is disclosed for forming an epitaxial layer on a front side of a substrate formed of a monocrystalline material, using a chemical vapor deposition system. In this method, a plurality of gettering wafers formed of a gettering material are arranged in the CVD system, such that the front side of each substrate is facing one of the gettering wafers. Impurities present in the CVD system during formation of the epitaxial layer are gettered by the gettering wafers. Alternatively, a layer of a gettering material is deposited on a back side of each of the plurality of substrates, and the substrates are arranged such that the front side of each substrate is facing the backside of another of the substrates. In another embodiment, a layer of a gettering material is deposited on an interior surface of the CVD system. Impurities removed from the CVD system during epitaxial formation include oxygen, water vapor and other oxygen-containing contaminants.

Method for improving CVD film quality utilizing polysilicon getterer

A method of forming a self-aligned gettering region within an SOI substrate is provided. Specifically, the inventive method includes the steps of forming a disposable spacer on each vertical sidewall of a patterned gate stack region, the patterned gate stack region being formed on a top Si-containing layer of an SOI substrate; implanting gettering species into the top Si-containing layer not protected by the disposable spacer and patterned gate stack region; and removing the disposable spacer and annealing the implanted gettering species so as to convert said species into a gettering region.

Use of disposable spacer to introduce gettering in SOI layer

A process for fabricating an MOS device having a highly-localized halo region includes the formation of a first halo region at a first surface of a silicon substrate, and a second halo region at a second surface of the silicon substrate. The second surface of the silicon substrate is formed by anisotropically etching the first surface of the silicon substrate to remove a portion of the material from the substrate. Both the first and second halo regions are formed by low-energy ion implantation. For the fabrication of an n-channel device, boron is implanted at an energy of no more than about 1 keV. Upon implantation and a subsequent annealing process, the first and second halo regions form a continuous halo region within the semiconductor substrate.

Process for fabricating an MOS device having highly-localized halo regions

Doped structures containing diffusion barriers

A process for forming an ultra-shallow junction depth, doped region within a silicon substrate. The process includes forming a dielectric film on the substrate, then implanting an ionic dopant species into the structure. The profile of the implanted species includes a population implanted through the dielectric film and into the silicon substrate, and a peak concentration deliberately confined in the dielectric film in close proximity to the interface between the dielectric film and the silicon substrate. A high-energy, low-dosage implant process is used and produces a structure that is substantially free of dislocation loops and other defect clusters. An annealing process is used to drive the peak concentration closer to the interface, and some of the population of the originally implanted species from the dielectric film into the silicon substrate. A low thermal budget is maintained because of the proximity of the as-implanted peak concentration to the interface and the presence of species implanted through the dielectric film and into the substrate.

Process of forming an ultra-shallow junction dopant layer having a peak concentration within a dielectric layer

A semiconductor structure having silicon dioxide layers of different thicknesses is fabricated by forming a sacrificial silicon dioxide layer on the surface of a substrate; implanting nitrogen ions through the sacrificial silicon dioxide layer into first areas of the semiconductor substrate; implanting chlorine and/or bromine ions through the sacrificial silicon dioxide layer into second areas of the semiconductor substrate where silicon dioxide having the highest thickness is to be formed; removing the sacrificial silicon dioxide layer; and then growing a layer of silicon dioxide on the surface of the semiconductor substrate. The growth rate of the silicon dioxide will be faster in the areas containing the chlorine and/or bromine ions and therefore the silicon dioxide layer will be thicker in those regions as compared to the silicon dioxide layer in the regions not containing the chlorine and/or bromine ions. The growth rate of the silicon dioxide will be slower in the areas containing the nitrogen ions and therefore the silicon dioxide layer will be thinner in those regions as compared to the silicon dioxide layer in the regions not containing the nitrogen ions. Also provided are structures obtained by the above process.

Method for fabricating different gate oxide thicknesses within the same chip

Ultra-shallow junction dopant layer having a peak concentration within a dielectric layer

Reduced scale structures of improved reliability and/or increased composition options are enabled by the creation and use of quantum conductive recrystallization barrier layers. The quantum conductive layers are preferably used in trench capacitors to act as recrystallization barriers.

Quantum conductive recrystallization barrier layers

A process for thermal oxidation of a semiconductor substrate comprising exposing the substrate to a chlorine plasma, and then heating the substrate in an oxidizing ambient. The substrate may comprise silicon, germanium, or a combination thereof. The heating step may further comprise heating at a temperature of between about 750.degree. C. and about 850.degree. C.

Process for modified oxidation of a semiconductor substrate using

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Hopewell Junction, NY, United States of America

Paul Andrew Ronsheim