International Business Machines Corporation

Infineon Technologies Ag

Patrick William Dehaven

Cyprian Emeka Uzoh

David Brian Mitzi

David Robert Medeiros

Daniel C Edelstein

Keith Kwong Hon Wong

Cyril Cabral, Jr

Kenneth Parker Rodbell

Kwong Hon Wong

Eric D Perfecto

Suryanarayana Kaja

Charles C Goldsmith

Michele S Legere

Lawrence Alfred Clevenger

Andrew Herbert Simon

Yun-Yu Wang

Sunfei Fang

Anthony Gene Domenicucci

Christopher Carr Parks

Lynne Marie Gignac

Horatio Seymour Wildman

Glen L Miles

Chester T Dziobkowski

Steven H Boettcher

Prabhat Tiwari

David Peter Klaus

Jeffery L Hurd

Carol L Stanis

James Manley Pollard, Iii

Chih-Chao Yang

Takeshi Nogami

Timothy Joseph Dalton

Christian Lavoie

Ronald G Filippi

Terry Allen Spooner

Stephen Mark Rossnagel

Takamasa Usui

Nivo Rovedo

James F White

Paul David Agnello

Tomio Katata

Anita Madan

Brett H Engel

Paul A Totta

Philip L Flaitz

Sadanand Vinayak Deshpande

Peter Stevens Locke

Domingo A Ferrer

Richard J Murphy

Tsong-Lin Tai

Arun Vijayakumar

Chi-Hua Yang

Hideaki Aochi

Hsiang-Jen Huang

J Daniel Mis

Chin-Chao Yang

Jeffrey L Hurd, Deceased

A method includes forming a first metal liner conformally along a sidewall and a bottom of a contact opening. A second metal liner is formed above and in direct contact with the first metal liner, a grain size of the first metal liner is larger than a grain size of the second metal liner. A barrier layer is formed above and in direct contact with the second metal liner and the contact opening is filled with a conductive material to form a middle-of-the-line contact.

Automatic capacitance tuning for robust middle of the line contact and silicide applications

The present invention provides a process for preparing a melt-processed organic-inorganic hybrid material including the steps of maintaining a solid organic-inorganic hybrid material at a temperature above the melting point but below the decomposition temperature of the organic-inorganic hybrid material for a period of time sufficient to form a uniform melt and thereafter, cooling the uniform melt to an ambient temperature under conditions sufficient to produce the melt-processed organic-inorganic hybrid material.

Low temperature melt-processing of organic-inorganic hybrid

A method of forming a diffusion barrier for use in semiconductor device manufacturing includes depositing, by a physical vapor deposition (PVD) process, an iridium doped, tantalum based barrier layer over a patterned interlevel dielectric (ILD) layer, wherein the barrier layer is deposited with an iridium concentration of at least 60 atomic % such that the barrier layer has a resulting amorphous structure.

Copper interconnect structure with amorphous tantalum iridium diffusion barrier

Embodiments of the present invention provide a method of fabricating a contact structure in a layer of dielectric material between a semiconductor device and a back-end-of-line interconnect. The method includes creating at least one contact opening in said layer of dielectric material; forming a first TiN film through a chemical-vapor deposition process, said first TiN film lining said contact opening; and forming a second TiN film through a physical vapor deposition process, said second TiN film lining said first TiN film. A contact structure fabricated according to embodiments of the invention is also provided.

Low resistance contact structure and fabrication thereof

A novel interlevel contact via structure having low contact resistance and improved reliability, and method of forming the contact via. The method comprises steps of: etching an opening through an interlevel dielectric layer to expose an underlying metal (Copper) layer surface; and, performing a low energy ion implant of an inert gas (Nitrogen) into the exposed metal underneath; and, depositing a refractory liner into the walls and bottom via structure which will have a lower contact resistance due to the presence of the proceeding inert gas implantation. Preferably, the inert Nitrogen gas reacts with the underlying exposed Copper metal to form a thin layer of CuN.

Method of forming low resistance and reliable via in inter-level dielectric interconnect

A method of forming a salicide on a semiconductor device includes depositing a first refractory metal layer over a silicon region of a substrate, depositing a near-noble metal layer over the first refractory metal layer, and depositing a second refractory metal layer over the near-noble metal layer. The semiconductor device is annealed in a first annealing process to form a silicide layer abutting the doped region of the semiconductor device. Un-reacted portions of the near-noble metal layer and the second refractory metal layer are removed. The device may be annealed in an optional second annealing process to convert the silicide layer to a low resistance phase silicide material. Junction leakage and bridging are minimized or eliminated by embodiments of the present invention, and a smoother silicided surface is achieved.

Salicide formation method

A process for controlling grain growth in the microstructure of thin metal films (e.g., copper or gold) deposited onto a substrate. In one embodiment, the metal film is deposited onto the substrate to form a film having a fine-grained microstructure. The film is heated in a temperature range of 70-100&deg; C. for at least five minutes, wherein the fine-grained microstructure is converted into a stable large-grained microstructure. In another embodiment, the plated film is stored, after the step of depositing, at a temperature not greater than &minus;20&deg; C., wherein the fine-grained microstructure is stabilized without grain growth for the entire storage period.

Device produced by a process of controlling grain growth in metal films

An electromigration-resistant copper film structure and the process for forming the structure. The film structure contains a high impurity content, is resistant to grain growth, and possesses superior metallurgical, thermo-mechanical, and electrical properties. The process comprises the steps of: (a) providing a seed layer at least indirectly on a substrate, the seed layer having an exposed surface; (b) immersing the substrate in a plating solution; (c) electrodepositing a copper-containing film on the exposed surface of the seed layer, the copper-containing film having a first surface; (d) maintaining the substrate in an immersed state within the plating solution; (e) electrodepositing a further copper-containing film from the plating solution onto the first surface; (f) removing the substrate from the plating solution; and (g) drying the substrate.

Electromigration-resistant copper microstructure

A process for forming a conductive contact having a flat interface. A layer containing niobium and titanium is deposited on a silicon substrate and the resulting structure is annealed in a nitrogen-containing atmosphere at about 500&deg; C. to about 700&deg; C. By this process, a flatter interface between silicide and silicon, which is less likely to cause junction leakage, is formed on annealing. The step of annealing also produces a more uniform bilayer, which is a better barrier against tungsten encroachment during subsequent tungsten deposition. Larger silicide grains are also formed so that fewer grain boundaries are produced, reducing metal diffusion in grain boundaries. The process can be used to form contacts for very small devices and shallow junctions, such as are required for current and future semiconductor devices.

Process for manufacturing a contact barrier

An interconnect structure and barrier layer for electrical interconnections is described incorporating a layer of TaN in the hexagonal phase between a first material such as Cu and a second material such as Al, W, and PbSn. A multilayer of TaN in the hexagonal phase and Ta in the alpha phase is also described as a barrier layer. The invention overcomes the problem of Cu diffusion into materials desired to be isolated during temperature anneal at 500&deg; C.

Thin film metal barrier for electrical interconnections

A process for controlling grain growth in the microstructure of thin metal films (e.g., copper or gold) deposited onto a substrate. In one embodiment, the metal film is deposited onto the substrate to form a film having a fine-grained microstructure. The film is heated in a temperature range of 70-100&deg;C. for at least five minutes, wherein the fine-grained microstructure is converted into a stable large-grained microstructure. In another embodiment, the plated film is stored, after the step of depositing, at a temperature not greater than &minus;20&deg; C., wherein the fine-grained microstructure is stabilized without grain growth for the entire storage period.

Process of controlling grain growth in metal films

Copper is plated onto a substrate by plating a layer of copper onto the substrate to provide a maximum thickness of about 350 nanometers, followed by subjecting the copper coated substrate to an oxygen containing gaseous ambient in order to roughen the copper surface. Next, a second layer of copper is electroplated onto the structure to provide the desired thickness. The texture of the second layer of copper is independent of the underlayer of copper and has a random or at least substantially random texture.

Method for controlling the texture and microstructure of plated copper and plated structure

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Poughkeepsie, NY, United States of America

Patrick William Dehaven