Via Technologies, Inc.

Patrick Lin

Wei-Pin Chen

The present invention relates to a structure and a method of data update in a cache memory inside a local processor, which uses the feature of cache control. A buffer block of a header buffer is mapped to a memory space at several different address sectors addressed by the local processor. Whenever the local processor attempts to access the internal cache memory, cache missing will occur so that a local processor will be forced to alternatively request new data from buffer blocks of a header buffer in a HCA. Consequently, the whole block is loaded into cache memory. This does not only boost cache update performance but also accelerates packet access.

Structure and method of cache memory data update

A ball-grid array (BGA) IC packaging frame of the invention includes a plurality of ball-grid array tin balls formed on the rear surface of a BGA package and a plurality of supporting pads formed on the surrounding of the rear surface. The designed supporting pads can efficiently prevent a non-contact soldering and a short circuit when a BGA IC is mounted on a PCB during manufacturing.

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Hsin Tien, Taiwan

Patrick Lin