Intel Corporation

Google Inc.

Patrick H Keys

Stephen M Cea

Aaron D Lilak

Rishabh Mehandru

Seiyon Kim

Roza Kotlyar

Tahir Ghani

Ravi Pillarisetty

Patrick R Morrow

James S Clarke

Sean T Ma

Hubert C George

Cory E Weber

Roman Caudillo

Jeanette M Roberts

Nicole K Thomas

Zachary R Yoscovits

Kanwaljit Singh

Michael G Haverty

Sadasivan Shankar

Payam Amin

Jack T Kavalieros

Anand S Murthy

Glenn A Glass

Rafael Rios

Biswajeet Guha

Kelin J Kuhn

Annalisa Cappellani

Dax M Crum

Justin R Weber

Harry Gomez

Susmita Ghose

Mayank Sahni

David J Michalak

Lester Lampert

Jack Hwang

Anupama Bowonder

Aaron A Budrevich

Stephanie A Bojarski

Sridhar Govindaraju

Leonard C Pipes

Hei Kam

Florian Luethi

Sayed Hasan

Ted E Cook, Jr

Seok-Hee Lee

Chad D Lindfors

Tzu-Min Ou

Jack Yaung

Seahee Hwangbo

Ted Cook, Jr

Gate-all-around integrated circuit structures having underlying dopant-diffusion blocking layers are described. For example, an integrated circuit structure includes a vertical arrangement of horizontal nanowires above a fin. The fin includes a dopant diffusion blocking layer on a first semiconductor layer, and a second semiconductor layer on the dopant diffusion blocking layer. A gate stack is around the vertical arrangement of horizontal nanowires. A first epitaxial source or drain structure is at a first end of the vertical arrangement of horizontal nanowires. A second epitaxial source or drain structure is at a second end of the vertical arrangement of horizontal nanowires.

Gate-all-around integrated circuit structures having underlying dopant-diffusion blocking layers

Disclosed herein are lateral gate material arrangements for quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack; and a gate above the quantum well stack, wherein the gate includes a gate electrode, the gate electrode includes a first material proximate to side faces of the gate and a second material proximate to a center of the gate, and the first material has a different material composition than the second material.

Lateral gate material arrangements for quantum dot devices

Fin doping, and integrated circuit structures resulting therefrom, are described. In an example, an integrated circuit structure includes a semiconductor fin. A lower portion of the semiconductor fin includes a region having both N-type dopants and P-type dopants with a net excess of the P-type dopants of at least 2E18 atoms/cm. A gate stack is over and conformal with an upper portion of the semiconductor fin. A first source or drain region is at a first side of the gate stack, and a second source or drain region is at a second side of the gate stack opposite the first side of the gate stack.

Fin doping and integrated circuit structures resulting therefrom

Stacked finFET structures including a fin having at least a first layer of semiconductor material stacked over or under a second layer of semiconductor material. The first and second layers may include a Group IV semiconductor material layer and a Group III-V semiconductor material layer, for example. A stacked finFET may include an N-type finFET stacked over or under a P-type finFET, the two finFETs may have channel portions within the different semiconductor material layers. Channel portions of the first and second layers of semiconductor material may be coupled to separate gate electrodes that are vertically aligned. Channel portions of the first and second layers of semiconductor material may be vertically separated by subfin portions of the first and second layers. Different layers of dielectric material adjacent to the subfin portions may improve electrical isolation between the channel portions, for example as a source of fixed charge or impurity dopants.

Vertically stacked finFETs and shared gate patterning

Nanowire structures having wrap-around contacts are described. For example, a nanowire semiconductor device includes a nanowire disposed above a substrate. A channel region is disposed in the nanowire. The channel region has a length and a perimeter orthogonal to the length. A gate electrode stack surrounds the entire perimeter of the channel region. A pair of source and drain regions is disposed in the nanowire, on either side of the channel region. Each of the source and drain regions has a perimeter orthogonal to the length of the channel region. A first contact completely surrounds the perimeter of the source region. A second contact completely surrounds the perimeter of the drain region.

Nanowire structures having wrap-around contacts

An apparatus is provided which comprises: a plurality of nanowire transistors stacked vertically, wherein each nanowire transistor of the plurality of nanowire transistors comprises a corresponding nanowire of a plurality of nanowires; and a gate stack, wherein the gate stack fully encircles at least a section of each nanowire of the plurality of nanowires.

Removal of a bottom-most nanowire from a nanowire device stack

Multiple strain states in epitaxial transistor channel material may be achieved through the incorporation of stress-relief defects within a seed material. Selective application of strain may improve channel mobility of one carrier type without hindering channel mobility of the other carrier type. A transistor structure may have a heteroepitaxial fin including a first layer of crystalline material directly on a second layer of crystalline material. Within the second layer, a number of defected regions of a threshold minimum dimension are present, which induces the first layer of crystalline material to relax into a lower-strain state. The defected regions may be introduced selectively, for example a through a masked impurity implantation, so that the defected regions may be absent in some transistor structures where a higher-strain state in the first layer of crystalline material is desired.

Multiple strain states in epitaxial transistor channel through the incorporation of stress-relief defects within an underlying seed material

Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack including a quantum well layer and a barrier layer; a first gate metal above the quantum well stack, wherein the barrier layer is between the first gate metal and the quantum well layer; and a second gate metal above the quantum well stack, wherein the barrier layer is between the second gate metal and the quantum well layer, and a material structure of the second gate metal is different from a material structure of the first gate metal.

Quantum dot devices with strain control

Quantum dot devices, and related systems and methods, are disclosed herein. In some embodiments, a quantum dot device may include a quantum well stack; a plurality of first gates above the quantum well stack; and a plurality of second gates above the quantum well stack; wherein the plurality of first gates are arranged in electrically continuous first rows and the plurality of second gates are arranged in electrically continuous second rows parallel to the first rows. Quantum dot devices according to various embodiments of the present disclosure are based on arranging first and second gates in hexagonal/honeycomb arrays.

Hexagonal arrays for quantum dot devices

Methods and apparatus to remove epitaxial defects in semiconductors are disclosed. A disclosed example multilayered die structure includes a fin having a first material, where the fin is epitaxially grown from a first substrate layer having a second material, and where a defect portion of the fin is etched or polished. The disclosed example multilayered die structure also includes a second substrate layer having an opening through which the fin extends.

Methods and apparatus to remove epitaxial defects in semiconductors

A transistor including a gate stack and source and drain on opposing sides of the gate stack; and a first material and a second material on the substrate, the first material disposed between the substrate and the second material and the channel of the transistor is defined in the second material between the source and drain, wherein the first material and the second material each include an implant and the implant includes a greater solubility in the first material than in the second material. A method for forming an integrated circuit structure including forming a first material on a substrate; forming a second material on the first material; introducing an implant into the second material, wherein the implant includes a greater solubility in the first material than in the second material; annealing the substrate; and forming a transistor on the substrate, the transistor including a channel including the second material.

Retrograde transistor doping by heterojunction materials

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Portland, OR, United States of America

Patrick H Keys