Agency for Science, Technology and Research

Advanced Micro Foundry Pte. Ltd.

Patrick Guo Qiang Lo

Ranganathan Nagarajan

Narayanan Balasubramanian

Wei Yip Loh

Shawn Yohanes Siew

Larry Lian Xi Jia

A hybrid photonic chip comprising a plurality of semiconductor materials arranged to define a chip providing a function, wherein at least a first part of the chip is formed of materials which can be fabricated using a CMOS technique; and at least a second part of the chip which comprises non-linear crystal material and is not subjected to etching process; wherein the second part of the chip in conjunction with the first part is configured to support a propagating low loss single mode.

Hybrid CMOS compatible electro-optic device

A method is described to form a MOSFET with a fully silicided gate electrode and fully silicided, raised S/D elements that are nearly coplanar to allow a wider process margin when forming contacts to silicided regions. An insulator block layer is formed over STI regions and a conformal silicidation stop layer such as Ti/TiN is disposed on the insulator block layer and active region. A polysilicon layer is deposited on the silicidation stop layer and is planarized by a CMP process to form raised S/D elements. An oxide hardmask on the gate electrode is removed to produce a slight recess between the spacers. A silicidation process yields a gate electrode and raised S/D elements comprised of NiSi. Optionally, a recess is formed in the substrate between an insulator block mask and spacer and a Schottky barrier is used instead of a silicidation stop layer to form a Schottky Barrier MOSFET.

Fully salicided (FUCA) MOSFET structure

Fully salicided (FUSA) MOSFET structure

Growing community of inventors

Singapore, Singapore

Patrick Guo Qiang Lo