University of California

Patrick G Kofron

Scott Daniel Hector

John S Taylor

Alan R Stivers

Pawitter J S Mangat

Matthew A Thompson

William Man-Wai Tong

A process for creating a mask substrate involving depositing: 1) a coating on one or both sides of a low thermal expansion material EUVL mask substrate to improve defect inspection, surface finishing, and defect levels; and 2) a high dielectric coating, on the backside to facilitate electrostatic chucking and to correct for any bowing caused by the stress imbalance imparted by either other deposited coatings or the multilayer coating of the mask substrate. An film, such as TaSi, may be deposited on the front side and/or back of the low thermal expansion material before the material coating to balance the stress. The low thermal expansion material with a silicon overlayer and a silicon and/or other conductive underlayer enables improved defect inspection and stress balancing.

Growing community of inventors

San Jose, CA, United States of America

Patrick G Kofron