Redpine Signals, Inc.

Silicon Laboratories Inc.

Ceremorphic, Inc.

Partha Sarathy Murali

Subba Reddy Kallam

Venkat Mattela

Karthik Vaidyanathan

Logeshwaran Vijayan

Dharani Naga Sailaja Sankabathula

Ajay Mantha

Venkata Siva Prasad Pulagam

Sundaram Vanka

Nagaraja Reddy Anakala

Deepu Vasudevan Nair

Suresh Kumar Vagvala

Varun Ramchandani

Nagaraj Reddy Anakala

Phanimithra Gangalakurti

Suryanarayana Varma Nallaparaju

Prem Kiran Nerella

Sriram Mudulodu

Satya Rao

Phanimithra Gangalakurthi

Akhil Soni

Anusha Biyyani

Vaidyanathan Karthik

Venkatesh Vinjamuri

InduShekhar Ayyalasomayajula

Shahabuddin Mohammed

Kriyangbhai Vinodbhai Shah

Rahul Kumar Gurram

Venkata Rao Gunturu

Mani Kumar Kothamasu

Narasimhan Venkatesh

Sailaja Dharani Naga Sankabathula

Venkat Rao Gunturu

Manoj Kumar Medam

Paul Reuben Vincent

Seok-Bae Park

Paul Rueuben Vincent

SuryaNarayana Varma Nallajaraju

Sivaram Trikutam Alukuru

Chandra Sekhar Ponnamanda Venkata

Suchin Gupta

Divyaxi Rudani

Karthik Viadyanathan

InduSheknar Ayyalasomayajula

Kashiviswanath Nethi

A multi-thread communication system has several communications processors operative over a single interface for transmitting and receiving packets. The multi-thread communications processor is operative to sequentially handle multiple thread processes for each communications processor on a cycle by cycle basis according to a thread map register which determines the order of execution and how many cycles of a particular thread occur during a canonical interval.

Communication processor handling communications protocols on separate threads

A communication processor is operative to adapt the thread allocation to communications processes handled by a multi-thread processor on an instruction by instruction basis. A thread map register controls the allocation of each processor cycle to a particular thread, and the thread map register is reprogrammed as the network process loads for a plurality of communications processors such as WLAN, Bluetooth, Zigbee, or LTE have load requirements which increase or decrease. A thread management process may dynamically allocate processor cycles to each respective process during times of activity for each associated communications process.

Multi-thread wireless communications processor with granular thread processes

A mesh receiver has a wakeup receiver for reception of a wakeup sequence formed by keyed RF or a sequence of wireless packets and gaps, a transmitter forming low speed RF wakeup sequence to other mesh stations, a mesh receiver for reception of high speed WLAN packets, the transmitter sending a wireless ACK packet in response to a wakeup sequence, the mesh receiver thereafter receiving wireless packets from a remote station, the mesh transmitter sending an ACK, the mesh station thereafter identifying a next hop station, and sending a wakeup sequence to that station, after receipt of an ACK, sending the data, the mesh receiver and mesh transmitter thereafter going to sleep.

Ultra low power mesh network

A bitstream modifier is operative on a packet which uses repetition coding. The bitstream modifier increases randomness of the data in a deterministic manner such that spectral spurs from repetition coding are greatly reduced, thereby providing greater available transmit power. In another example of the invention, baseband samples of a header and/or payload for a Bluetooth packet are modified by a canonical sequence with a low slew rate for data such that the variations in frequency may be tracked by a receiver and the transmitted spectral spurs reduced.

Apparatus and method to reduce spectral peaks in Bluetooth communications

The present invention is an controller for dynamically allocating RAM between powersave code copied from ROM and transient RAM memory used for storing packets. When the utilization of the transient RAM memory is low, code segments are copied from ROM and executed from RAM using a RAM pointer table which is updated after the code segments are copied over from ROM, and when the utilization of the transient RAM memory is high, code segments are deallocated from RAM and the pointer table is updated to point to the corresponding location in flash ROM.

System and method for flash and RAM allocation for reduced power consumption in a processor

A multi-thread processor has a canonical thread map register which outputs a sequence of thread_id values indicating a current thread for execution. The thread map register is programmable to provide granularity of number of cycles of the canonical sequence assigned to each thread. In one example of the invention, the thread map register has repeating thread identifiers in a sequential or non-sequential manner to overcome memory latency and avoid thread stalls. In another example of the invention, separate interrupt tasks are placed on each thread to reduce interrupt processing latency.

Multi-threaded processor with thread granularity

A communications processor is operative in a plurality of modes including at least a high performance mode, a power savings mode with lower computational capability, and a shutdown mode with a wakeup capability. A memory for the communications processor has a high speed segment and a low speed segment, the high speed segment and low speed segment respectively on a high speed data bus and a low speed data bus, the high speed data bus and low speed data bus coupled by a bidirectional bridge.

Method and apparatus for selectable high performance or low power processor system

Ultra-low power mesh network

A task processor has a low power connectivity processor and a high performance applications processor. Software processes have a component operative on a connectivity processor and a component operative on an applications processor. The low power connectivity processor is coupled to a low power front end for wireless packets and the high performance applications processor is coupled to a high performance front end. A power controller is coupled to the low power front end and enables the applications processor and high performance front end when wireless packets which require greater processing capacity are received, and removes power from the applications processor and high performance front end at other times.

Dual processor system for reduced power application processing

A transmit/receive signal processor for Wireless Local Area Network (WLAN) and Bluetooth has selectable signal processing elements for mixers, Intermediate Frequency (IF) filters, transmit power amplifiers, and clock sources which are suitable for either Bluetooth or WLAN signal processing. The operating mode of the signal processor is selected to be one of Wireless High Performance, Wireless Low Power, Bluetooth High Performance or Bluetooth Low power, and the signal processing modules are selected to provide performance or power requirements using selected modules.

Multiplexed signal processing system for bluetooth and WLAN transceiver

A communications system has a low power connectivity processor and a high performance applications processor. The low power connectivity processor is coupled to a low power front end for wireless packets and the high performance applications processor is coupled to a high performance front end. A power controller is coupled to the low power front end and enables the applications processor and high performance front end when wireless packets which require greater processing capacity are received, and removes power from the applications processor and high performance front end at other times.

Dual processor power saving architecture communications system

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San Jose, CA, United States of America

Partha Sarathy Murali