Magma Design Automation, Inc.

Synopsys, Inc.

Partha Das

Arvind Srinivasan

Samit Chaudhuri

Yunjian (William) Jiang

Yinghua Li

Joy Banerjee

A method of optimizing clock-gated circuitry in an integrated circuit (IC) design is provided. A plurality of signals which feed into enable inputs of a plurality of clock gates is determined, where the clock gates gate a plurality of sequential elements in the IC design. Combinational logic which is shared among the plurality of signals is identified. The clock-gated circuitry is transformed into multiple levels of clock-gating circuitry based on the shared combinational logic.

Multi-level clock gating circuitry transformation

A power optimization method of deriving gated circuitry in a synthesized netlist of an integrated circuit (IC) design is provided. A block in the synthesized netlist is identified as an idle candidate block. Sub-blocks on the chip are clustered into a cluster. For the cluster, a clock gating structure optimized for power savings is determined, based on the idle candidate block. One or more inflexible clock gates are inserted in the netlist according to the clock gate structure.

Method for automatic clock gating to save power

Method for optimized automatic clock gating

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Kolkata, India

Partha Das