Stmicroelectronics S.r.l.

Sgs-thomson Microelectronics S.r.l.

Micron Technology Incorporated

Other

Commissariat a L'energie Atomique Et Aux Energies Alternatives

Sgs Microelettronica Spa

Stmicroelectronics (crolles 2) Sas

Western Digital (fremont), Inc.

Commissariat a L'energie Atomique Et Aux Energies

Stmicroelectronics (grenoble 2) Sas

Paolo Giuseppe Cappelletti

Alfonso Maurelli

Emilio Camerlenghi

Gabriele Navarro

Marcello Mariani

Roberto Gastaldi

Bruno Vajana

Carlo Riva

Giulio Casagrande

Luca Pividori

Alessandro Grossi

Giuseppe Corda

Leonardo Ravazzi

Paola Zabberoni

Andrea Redaelli

Livio Baldi

Carmela Cupeta

Paolo Ghezzi

Nicola Zatelli

Silvia Lucherini

Fabio Pellizzer

Rino Micheloni

Giovanni Campardo

Giorgio Servalli

Guido Torelli

Xizeng Shi

Kyusik Sin

Roberto Bez

Matthew R Gibbons

Marco Olivo

Mauro Luigi Sali

Hugh Craig Hiner

Cristiano Calligaro

Alessandro Manstretta

William D Jensen

Tecla Ghilardi

Loris Vendrame

Daniele Cantarelli

Bruno Ricco

Fausto Piazza

David Esseni

Franco Maggioni

Bruno Beverina

An electronic cell includes an integrated stack of structures including, successively: a first electrode; an ovonic threshold switch layer below the first electrode; and a fixed resistor below the ovonic threshold switch layer. A second electrode may be included between fixed resistor and the ovonic threshold switch layer. A memory layer, for example a phase change material layer, a resistive random-access memory layer or a magneto-resistive random-access memory layer, may be included between the first electrode and the ovonic threshold switch layer.

Switching cell with direct contact to fixed resistor element

A memory cell includes a substrate with a semiconductor region and an insulating region. A first insulating layer extends over the substrate. A phase change material layer rests on the first insulating layer. The memory cell further includes an interconnection network with a conductive track. A first end of a first conductive via extending through the first insulating layer is in contact with the phase change material layer and a second end of the first conductive via is in contact with the semiconductor region. A first end of a second conductive via extending through the first insulating layer is in contact with both the phase change material layer and the conductive track, and a second end of the second conductive via is in contact only with the insulating region.

Phase change memory

Phase-change memory cells and methods of manufacturing and operating phase-change memory cells are provided. In at least one embodiment, a phase-change memory cell includes a heater and a stack. The stack includes at least one germanium layer or a nitrogen doped germanium layer, and at least one layer of a first alloy including germanium, antimony, and tellurium. A resistive layer is located between the heater and the stack.

Phase-change memory cell

A phase-change memory cell includes, in at least a first portion, a stack of at least one germanium layer covered by at least one layer made of a first alloy of germanium, antimony, and tellurium In a programmed state, resulting from heating a portion of the stack to a sufficient temperature, portions of layers of germanium and of the first alloy form a second alloy made up of germanium, antimony, and tellurium, where the second alloy has a higher germanium concentration than the first alloy.

Memory device

A phase-change memory cell is formed by a heater, a crystalline layer disposed above the heater, and an insulating region surrounding sidewalls of the crystalline layer. The phase-change memory cell supports programming with a least three distinct data levels based on a selective amorphization of the crystalline layer.

Memory cell

A phase-change memory cell includes, in at least a first portion, a stack of at least one germanium layer covered by at least one layer made of a first alloy of germanium, antimony, and tellurium. In a programmed state, resulting from heating a portion of the stack to a sufficient temperature, portions of layers of germanium and of the first alloy form a second alloy made up of germanium, antimony, and tellurium, where the second alloy has a higher germanium concentration than the first alloy.

Some embodiments include semiconductor constructions having stacks containing electrically conductive material over dielectric material. Programmable material structures are directly against both the electrically conductive material and the dielectric material along sidewall surfaces of the stacks. Electrode material electrically coupled with the electrically conductive material of the stacks. Some embodiments include methods of forming memory cells in which a programmable material plate is formed along a sidewall surface of a stack containing electrically conductive material and dielectric material.

Semiconductor constructions and methods of forming memory cells

In some embodiments, a gate structure with a spacer on its side may be used as a mask o form self-aligned trenches in microelectronic memory, such as a flash memory. A first portion of the gate structure may be used to form the mask, together with sidewall spacers, in some embodiments. Then, after forming the shallow trench isolations, a second portion of the gate structure may be added to form a mushroom shaped gate structure.

Shallow trench isolation for a memory

In some embodiments, a gate structure with a spacer on its side may be used as a mask to form self-aligned trenches in a microelectronic memory, such as a flash memory. A first portion of the gate structure may be used to form the mask, together with sidewall spacers, in some embodiments. Then, after forming the shallow trench isolations, a second portion of the gate structure may be added to form a mushroom shaped gate structure.

An integrated transistor device is formed in a chip of semiconductor material having an electrical-insulation region delimiting an active area accommodating a bipolar transistor of vertical type and a MOSFET of planar type, contiguous to one another. The active area accommodates a collector region; a bipolar base region contiguous to the collector region; an emitter region within the bipolar base region; a source region, arranged at a distance from the bipolar base region; a drain region; a channel region arranged between the source region and the drain region; and a well region. The drain region and the bipolar base region are contiguous and form a common base structure shared by the bipolar transistor and the MOSFET. Thereby, the integrated transistor device has a high input impedance and is capable of driving high currents, while only requiring a small integration area.

Transistor structure with high input impedance and high current capability

A method for manufacturing electrically non-active structures for an electronic circuit integrated on a semiconductor substrate is provided, with the electronic circuit including first and second electrically active structures. The method includes inserting the electrically non-active structures in the electronic circuit to make uniform a surface above the semiconductor substrate. The inserting includes identifying, among the electrically non-active structures, a first group of electrically non-active structures to be adjacent the first and second electrically active structures, and identifying, among the electrically non-active structures, a second group of electrically non-active structures not adjacent to the first and second electrically active structures. The method further includes defining, on the semiconductor substrate, the first and second groups of electrically non-active structures through different photolithographic steps.

Manufacturing method for non-active electrically structures in order to optimize the definition of active electrically structures in an electronic circuit integrated on a semiconductor substrate and corresponding circuit

Growing community of inventors

Seveso, Italy

Paolo Giuseppe Cappelletti